DRAM cell structure with buried surrounding capacitor and...

Details DRAM cell structure with buried surrounding capacitor and... DRAM cell structure with buried surrounding capacitor and...

2007-04-24

2007-04-24

Fourson, George R. (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S300000, C257S301000, C257S516000, C257S532000, C257SE27092, C257SE29346, C438S155000, C438S244000

Reexamination Certificate

active

11062563

ABSTRACT:
A memory device that includes a semiconductor substrate, and an array of memory cells, each cell being electrically isolated from adjacent cells and including an island formed from the substrate, the island having a top portion and at least one sidewall portion, and being spaced apart from other islands by a bottom surface on the substrate, a capacitor formed contiguous with the sidewall portion, and a transistor formed on the top portion of the island, the transistor including a gate oxide layer formed on a surface of the top portion, a gate formed on the gate oxide layer, and a first and a second diffused regions formed in the top portion, the first diffused region being spaced apart from the second diffused region.

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patent: 2002/0127811 (2002-09-01), Noble
patent: 2002/0191455 (2002-12-01), Richter et al.

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