DRAM cell refreshment method and circuit

Details DRAM cell refreshment method and circuit DRAM cell refreshment method and circuit

2002-06-27

2004-10-05

Tran, M. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S149000

Reexamination Certificate

active

06801467

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to DRAMs, and more specifically to a method and a device enabling increasing the refreshment voltage of the cells in a DRAM.
2. Discussion of the Related Art
A DRAM includes memory cells in which a logic information “1” or “0” can be stored. Each memory cell includes a capacitor in which a predetermined voltage chosen from among two values is stored according to whether a 1 or a 0 is memorized in the cell. The capacitor of a memory cell can never be perfectly isolated, and the voltage on the capacitor is not steady and declines along time. After a predetermined duration, called the retention period, the voltage stored in the capacitor of a memory cell may thus be too small to be readable. To avoid loss of the information stored in each capacitor, the voltage stored in each capacitor is periodically refreshed. For this purpose, a read device periodically compares the voltage stored in each capacitor with a reference voltage, after which it charges each capacitor to one or the other of the predetermined voltages according to whether the compared voltage is greater or smaller than the reference voltage.
FIG. 1
schematically shows a conventional DRAM structure arranged in rows and columns. A single memory cell Mi of the memory is shown. Memory cell Mi includes a capacitor Ci having a first terminal connected to a reference voltage Vp. A second terminal of capacitor Ci is connected to a bit line BL via a switch Si. The second terminal of capacitor Ci forms an input/output terminal of memory cell Mi. The control terminal of switch Si forms a terminal of selection of memory cell Mi, and receives a selection signal WLi. Bit line BL is connected to an input terminal of a read device
2
via a switch
4
. Device
2
includes two identical inverters
6
and
8
assembled in antiparallel. Input I
6
of inverter
6
, connected to the output of inverter
8
, forms the input terminal of device
2
. The output of inverter
6
is connected to input I
8
of inverter
8
. A high supply terminal of inverters
6
and
8
is connected to a positive supply voltage Vdd via a switch
10
. Switch
10
receives a control signal RESTORE. A low supply terminal of inverters
6
and
8
is connected to a ground voltage GND via a switch
12
. Switch
12
receives a control signal SENSE. The input of inverter
8
is connected to a reference bit line BLref via a switch
14
. Switches
4
and
14
receive a same control signal PASS. Reference bit line BLref is provided to exhibit a stray capacitance identical to that of bit line BL. A reference memory cell Mref, having a structure identical to that of memory cell M, is connected to reference bit line BLref. Cell Mref includes a capacitor Cref connected to bit line BLref via a switch Sref. Capacitor Cref is identical to capacitor Ci. The terminal of selection of memory cell Mref receives a control signal WLref. A precharge circuit
16
, controlled by a signal PRA, is connected to terminals I
6
and I
8
. Precharge circuits, not shown, controlled by signal PRA, are connected to lines BL and BLref and to the input/output terminal of memory cell Mref. Control signals WLi, WLref, PASS, RESTORE, and PRA are generated by control means not shown.
Bit lines BL and BLref are connected to a refreshment device
18
. Device
18
includes P-channel MOS transistors
20
and
22
, having their respective drains connected to lines BL and BLref. The sources of transistors
20
and
22
are interconnected. The gate of transistor
20
is connected to the drain of transistor
22
and the gate of transistor
22
is connected to the drain of transistor
20
. A P-channel transistor
24
has its source connected to a supply voltage Vcc greater than voltage Vdd and its drain connected to the sources of transistors
20
and
22
. The gate of transistor
24
receives a control signal noBOOST.
FIGS. 2A through 2H
illustrates the variation along time of the voltages of bit lines BL and BLref, and of signals WLi, WLref, SENSE, RESTORE, PASS, noBOOST, and PRA in a step of refreshment of memory cell Mi. At an initial time t
0
, signals WLi and WLref are at 0 and capacitors Ci and Cref of memory cells Mi and Mref are isolated from lines BL and BLref. Signal PASS is at 0 and terminals I
6
and I
8
are isolated from lines BL and BLref. Signals SENSE and RESTORE are at 0 and inverters
6
and
8
are deactivated. Signal PRA is at 1 and block
16
forces the voltages of terminals I
6
and I
8
to a voltage Vdd/2. Similarly, precharge circuits, not shown, force bit lines BL and BLref to voltage Vdd/2, and the input/output terminal of cell Mref to a reference voltage which is considered, for simplification, to be equal to Vdd/2.
At a time t
1
, signal PRA is brought to 0. The precharge circuits are then deactivated.
At a time t
2
, signals WLi, WLref, and PASS are brought to 1. Capacitors Ci and Cref are then respectively connected to terminals I
6
and I
8
. Bit line BL and terminal I
6
each exhibit a mainly capacitive predetermined impedance. From time t
2
, the charges stored in capacitor Ci distribute between capacitor Ci and the stray capacitances of line BL, of terminal I
6
, and of the gate of transistor
22
.
FIG. 2
illustrates an example in which a voltage Vdd/2+&Dgr;V is stored in capacitor Ci at a time t
2
. After time t
2
, the charges stored in capacitor Ci distribute between capacitor Ci and the stray capacitances of bit line BL, of terminal I
6
, and of the gate of transistor
22
. Because of the charge transferred to the stray capacitances, the terminal I
6
is thus brought to a voltage Vdd/2+&dgr;V smaller than voltage Vdd/2+&Dgr;V. Terminal I
8
, connected to line BLref and to capacitor Cref, remains at voltage Vdd/2.
At a time t
3
, signal SENSE is brought to 1 to turn switch
12
on. The low supply terminals of inverters
6
and
8
are then connected to voltage GND. As a response to voltage Vdd/2+&dgr;V of terminal I
6
, inverter
6
forces terminal I
8
and line BLref to voltage GND.
At a time t
4
, signal RESTORE is brought to 1 to turn switch
10
on. Inverters
6
and
8
are then supplied by voltage Vdd, and inverter
8
forces terminal I
6
and line BL to voltage Vdd. Memory cell Mi is then recharged to voltage Vdd. Technological progress and the increase in memory circuit integration especially causes a reduction in the size of the transistors (not shown) forming inverters
6
and
8
, and a decrease in supply voltage Vdd of these transistors. Now, a memory cell refreshed with too small a voltage Vdd is rapidly discharged, that is, it soon becomes unable to provide a sufficient voltage Vdd/2+&Dgr;V to control inverter
6
at time t
3
. Device
18
is provided to pull up the refreshment voltage of memory cell Mi.
At a time t
5
, signal noBOOST is brought to 0 to turn switch
24
on. Their transistors
20
and
22
must be matched so that their characteristics are identical and remain so, for example, in case of a variation in the operating temperature. In the example shown, the gate-source voltage of transistor
20
is more negative than the gate-source voltage of transistor
22
and transistor
20
becomes more conductive than transistor
22
. As a result, from time t
5
, line BL is quickly brought to voltage Vcc, which results in turning transistor
22
off. Line BLref thus remains at voltage GND. Memory cell Mi is then recharged to voltage Vcc, and the refreshment operation is over.
At a time t
6
, signal noBOOST is brought to 1 to make transistor
24
non-conductive and deactivate device
18
. At time t
6
, signal PASS is brought to 0, to turn off switches
4
and
14
and to isolate terminals I
6
and I
8
from lines BL and BLref, respectively. At time t
6
, signals SENSE and RESTORE are brought to 0 to turn off switches
10
and
12
and to deactivate inverters
6
and
8
. At time t
6
, signals WLi and WLref are brought to 0 to isolate capacitors Ci and Cref from lines BL and BLref.
At a time t
7
, precharge signal PRA is brought to 1 to control the pre

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