DRAM cell layout for node capacitance enhancement

Details DRAM cell layout for node capacitance enhancement DRAM cell layout for node capacitance enhancement

2000-06-23

2002-01-15

Quach, T. N. (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S301000, C257S302000

Reexamination Certificate

active

06339239

ABSTRACT:

CROSS REFERENCE TO RELATED APPLICATIONS
Aspects of the present invention are related to subject matter disclosed in co-pending applications entitled “Structure and Process for 6F2 Trench Capacitor DRAM Cell with Vertical MOSFET and 3F Bitline”, Ser. No. 09/602,426 filed Jun. 23, 2000 and, “Process Flow for Maskless Single Sided Buried Strap Formation of Vertical Cell”, Ser. No. 09/603,442, filed Jun. 23, 2000 each assigned to the assignee of the present invention.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to dynamic random access memory (DRAM) cells. More particularly, the present invention relates to the layout or positioning pattern of the deep trenches of cell pairs of an array of deep trench capacitor DRAM cells such as to increase the spacing between adjacent trenches of different cell pairs.
2. Background and Related Art
DRAM cells typically comprise a storage capacitor and insulated gate field effect transistor In order to achieve higher density DRAM devices, DRAM cells have been successively scaled down in size to the submicron range. However, as a result of the reduction in size, cell capacitance is reduced which reduction can lower the signed-to-noise ratio, increase refresh frequency, increase device error, etc.
Efforts to increase density and yet maintain the required level of capacitance has led to the development of the trench capacitor wherein the cell capacitor is formed in a trench structure within the silicon substrate. This not only reduces silicon surface area used for the capacitor, it also allows increased capacitor plate areas to be fabricated vertically without a corresponding increase in silicon surface area to thereby increase storage capacitance. Some such storage trench DRAM capacitors have been characterized as Merged Isolation and Node Trench (MINT) DRAM cells. To further increase capacitor plate areas without a corresponding increase in used silicon surface area, techniques have been developed called “bottling” wherein the lower portion of a deep trench is made larger than the upper portion creating a bottle-like shape or profile.
Even with the development of the trench capacitor and the deep trench bottle-shaped capacitor, increasing demand for higher density DRAM cell arrays has created a need for further bottle-shaped trench capacitance enhancement whereby the volume of the cavity in the lower portion of the storage trench may be further increased. It is apparent that the need for this increased capacitance is brought about, in part, by the fact that growing DRAM density tends to scale down cell size, and therefor trench plate size, while at the same time the voltage levels remain the same and the time between refresh for each cell increases as the number of cells increase.
However, it has been found that bottle-shaped trench capacitance enhancement is limited by the proximity of adjacent trenches and the necessity of maintaining the structural integrity of the trench capacitor. Typical prior art layout spacing between deep trench (DT) cells is 1F, 1F being the minimum lithographically-defined feature, where the minimum resolvable spatial pitch of an array of features would comprise 1F lines and 1F spaces with the minimum pitch thus being 2F. An F/3 radial enhancement through “bottling” in the lower portion of the trench results in a DT-to-DT spacing of F/3 at the widest point of the bottles. It has been found that to maintain structural integrity a DT-to-DT spacing of at least F/3 is required thereby limiting the extent of bottle enhancement to F/3.
Typical prior art efforts to improve cell layout, so as to maintain or increase feature spacing and reduce the silicon surface area utilized, have been directed to configuring cell shape and cell position so that cell access structure, such as wordline structure, is located, at least partially, over the trench capacitor. An example of such prior art effort is U.S. Pat. No. 6,004,844 entitled “Unit Cell Layout and Transfer Gate design For High Density DRAMs”.
SUMMARY OF THE INVENTION
In accordance with the teachings of the present invention, a DRAM cell layout pattern is provided such as to increase the spacing between adjacent trenches of different cell pairs over prior art MINT DRAM cells. More particularly, the individual DTs of an array of DRAM cells are positioned in the array so as to significantly increase the spacing between adjacent DT's. The positioning pattern of the DT array is such as to increase the spacing between the trench openings at the silicon surface to 1.3F to 1.7F. Such spacing between trench openings at the silicon surface permits bottle-shaped trench capacitance radial enhancement by a factor of approximately F/2, yet maintains the spacing between the widest points of the bottles to F/3.
The improved spacing between adjacent DTs, in accordance with the present invention, is achieved by offsetting in opposing directions, on each side of a bitline, the pair of DTs of cell pairs sharing a common bitline contact. A first offset pattern is carried out for all DTs along alternate bitlines. A second, opposite, offset pattern is carried out for all DTs along the remaining bitlines. The offset from the bitline is at an angle of approximately 45° and is such as to provide increased spacing to approximately 1.5F between the DTs of one cell pair and the DTs of adjacent cell pairs. In accordance with the present invention, such increased spacing permits greater “bottling” for node capacitance enhancement. The offset pattern also allows the pair of DTs of cell pairs sharing a common bitline contact to increase the overlap of the active area (AA) and DT where the cells employ a trench sidewall vertical transistor. Where the cells employ a planar transistor, the AA pattern may be lengthened to minimize electrical interaction between devices within the AA pattern.
Accordingly, it is an object of the present invention to provide node capacitance enhancement in deep trench DRAM cells.
It is another object of the present invention to provide DRAM cell node capacitance enhancement while at the same time maintaining the DT-to-DT spacing required for structural integrity of the capacitor.
It is yet another object of the present invention to provide an improved DRAM cell layout.
It is a further object of the present invention to provide a trench capacitor DRAM cell array layout which increases the trench-to-trench spacing for a given F dimension thereby allowing enhanced capacitance while maintaining DT and capacitor structural integrity.


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IBM Technical Disclosure Bulletin, entitled “High Density Vertical DRAM Cell”, Article No. 86A 62504, Oct. 1986, pp. 2335-2340.

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