DRAM cell having storage capacitor contact self-aligned to bit l

Details DRAM cell having storage capacitor contact self-aligned to bit l DRAM cell having storage capacitor contact self-aligned to bit l

1996-11-21

1999-11-30

Hardy, David B.

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257649, H01L 27108

Patent

active

059947306

ABSTRACT:
A DRAM cell (10) having a capacitor-over-bit line (COB) structure self-aligned to the word lines and bit lines is disclosed. Word lines (24) and bit lines (28) are formed with insulating structures that include insulating sidewalls. The word line insulating structure includes an etch barrier layer (46) that extends over a source region (18). A first interlayer dielectric (ILD) (48) insulates the word lines (24) from the bit lines (28) and a second ILD (60) insulates the bit lines from a cell capacitor. A capacitor contact hole (34), self-aligned with the bit lines and the word lines, is formed by etching through the first and second ILDs (48 and 60) to expose the etch barrier layer (46) over the source region (18). Portions of the bit line and word line exposed by the etch are protected by their respective insulating structures. The exposed etch barrier layer (46) over the source region (18) is cleared and a storage capacitor is formed having a contact that extends into the contact hole to make contact with the source region (18).

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"Fully Self-Aligned 6F.sup.2 Cell Technology for Low Cost 1 Gb DRAM," by Masami Aoki, et al., 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 22-23.
"3-Dimensional Stacked Capacitor Cell For 16M and 64M DRAMs," by T. Ema, et al., IEDM., 1988, pp. 592-595.

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