Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-05-21
2001-01-23
Hardy, David (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S532000
Reexamination Certificate
active
06177699
ABSTRACT:
BACKGROUND OF THE INVENTION
1. The Field of the Invention
The present invention relates to semiconductor devices and methods for their construction. More particularly, the present invention relates to capacitor design, transistor design and cell isolation methods used to reduce the surface area occupied by a DRAM cell. More specifically, the present invention merges capacitor design, transistor design and cell isolation methods by using existing isolation trench sidewalls to form a DRAM capacitor and a access transistor thus significantly increasing DRAM cell density over currently fabricated DRAM cells.
2. Background Art
Various DRAM capacitor designs have been employed to reduce the surface area occupied by a single DRAM cell. Early DRAM designs employed flat horizontal capacitor plates. Later designs, intended to conserve chip surface area, employed trenches or fin structures to form narrow dimension capacitors with some vertical contribution to the capacitor plate surface area.
In addition to the shape and size of the capacitor plates, the type of cell isolation contributes to the overall DRAM cell size. Traditionally, field oxide produced by the Local Oxidation of Silicon process (LOCOS) was used as cell isolation. Unfortunately, a field oxide must cover a fairly wide area in order to effectively isolate adjacent cells. Further, it is difficult to control the growth of field oxide. Therefore, field oxide often occupies a significant amount of the chip surface area.
More recently, trench isolation has been employed. This involves etching a narrow isolation trench around the active areas (cells) on the chip. The isolation trenches are then filled with oxide or other dielectric to effectively isolate adjacent active areas from one another. While trench isolation requires more process steps than LOCOS isolation (field oxide), trench isolation can be made much narrower than LOCOS isolation. Therefore, DRAMs employing trench isolation can be packed more densely than DRAMs employing LOCOS isolation.
In addition to isolation regions and capacitors, access transistors can also occupy a significant amount of wafer surface which limits the DRAM cell density. Typically, the gate structure and the source region of the access transistor are formed on the semiconductor substrate surface. Forming a portion of the access transistor directly above the isolation trench would significantly reduce the area of semiconductor substrate required for a DRAM cell.
In the continuing quest for higher density DRAMs, improved structures employing narrow dimension trench isolation and access transistors are still needed.
SUMMARY OF THE INVENTION
The present invention addresses this need by providing a DRAM cell where existing isolation trench sidewalls are used to form a DRAM capacitor and a portion of the access transistor is provided directly over the isolation trench sidewalls. Preferably, the access transistor is oriented vertically with respect to the plane of the integrated circuit. By integrating both the DRAM capacitor and access transistor formation with the DRAM cell isolation, the present invention may significantly increase DRAM cell density over currently fabricated DRAM cells.
In one aspect, the instant invention provides a DRAM cell including a vertically oriented pass (or access) transistor electrically coupled with a capacitor formed in an isolation trench on an active region of a semiconductor substrate. The isolation trench electrically isolates the DRAM cell from one or more adjacent DRAM cells.
The capacitor includes a first capacitor plate, a dielectric layer and a second capacitor plate. In a preferred embodiment, the first capacitor plate is defined by the semiconductor substrate at the wall of the isolation trench and has a substantially greater dopant concentration than immediately adjacent semiconductor substrate. The second capacitor plate is preferably defined by a conductive layer inside the isolation trench. The second capacitor plate occupies a portion of the isolation trench proximate to the access transistor. The conductive layer that may comprise the second capacitor plate is preferably doped polysilicon. It may be between about 200 Å and about 2000 Å thick.
The capacitor dielectric layer may be made from any suitable material that can be formed in the necessary size and shape. Suitable dielectric materials include at least one of SiO
2
, Si
3
N
x
, silicon oxynitride, ONO (SiO
2
/Si
3
N
x
/SiO
2
layered material), tantalum pentaoxide (Ta
2
O
5
), barium strontium titanate BaSrTiO
3
(“BST”) and piezoelectric lead zirconate titanate (“PZT”). Preferably, the dielectric layer comprises a material with a high dielectric constant (e.g., at least about 10) such as BST, PZT, or Ta
2
O
5
. In one specific embodiment, the dielectric layer is Ta
2
O
5
and is between about 20 and about 200 Å thick depending on the capacitor plate area.
The access transistor is preferably an MOS device that may have a drain electrically connected to the second capacitor plate and electrically isolated from the first capacitor plate. Preferably, the gate structure of the access transistor is provided over the capacitor in the trench isolation sidewalls and is vertically oriented with respect to the surface of the semiconductor substrate.
In the case of an MOS access transistor, the access transistor includes a semiconductor bulk section, a gate dielectric provided on a vertical sidewall of the semiconductor bulk region, a gate electrode formed on the gate dielectric, and a source region. The bulk semiconductor section is typically provided by a layer of epitaxial silicon which is deposited over the semiconductor substrate at locations outside the trench isolation. Silicide layers may optionally be provided on the gate electrode and source region. The electrical connection between the second capacitor plate and the drain of the access transistor is preferably provided as a high dopant concentration region in the semiconductor substrate and the epitaxial silicon layer.
In one embodiment, the isolation trench has a depth of at least about 0.3 &mgr;m. In another embodiment, the isolation trench has a width of at most about 0.5 &mgr;m. Preferably, the isolation trench is at least partially filled with a first dielectric material (e.g., silicon oxide). Typically, a second isolation dielectric (also silicon oxide in many cases) is provided over the first isolation dielectric material. In a specific embodiment, the gate structure of the access transistor is oriented parallel to the vertical sidewalls of the isolation trench and perpendicular to the semiconductor substrate.
In another aspect, the invention provides a method for forming a capacitor in an isolation trench and at least a portion of a vertically oriented access transistor in the area above the isolation trench in a integrated circuit. The process is characterized by forming an isolation trench about an active region in a semiconductor substrate, forming a capacitor in the isolation trench, filling the trench with a first isolation dielectric and forming at least a portion of the access transistor in the area above the isolation trench.
In one embodiment, the isolation trench includes both a capacitor dielectric and an isolation trench dielectric which occupy different areas of the isolation trench. This does not preclude embodiments where the isolation dielectric and the capacitor dielectric are made from the same material although one will generally want an isolation dielectric with a relatively low dielectric constant and a capacitor dielectric with a relatively high dielectric constant.
The capacitor may be formed by a process that may be characterized as having the following sequence: (a) forming a first capacitor plate in the semiconductor substrate immediately adjacent the sidewalls of the isolation trench; (b) forming a capacitor dielectric layer on part of the sidewalls of the isolation trench; and (c) forming a second capacitor plate on a part of the capacitor dielectric.
The first capacitor plate may be formed by
Liu Yauh-Ching
Perng Dung-Ching
Hardy David
LSI Logic Corporation
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