DRAM cell fabricated using a modified logic process and...

Details DRAM cell fabricated using a modified logic process and... DRAM cell fabricated using a modified logic process and...

1999-10-25

2003-01-21

Chaudhuri, Olik (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S412000

Reexamination Certificate

active

06509595

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to Dynamic Random Accessible Memory (DRAM). More particularly, this invention relates to DRAM fabricated by slightly modifying a conventional logic process. This invention further relates to the on-chip generation of precision voltages for the operation of DRAM embedded or fabricated using a conventional logic process.
2. Related Art
FIG. 1A
is a schematic diagram of a conventional DRAM cell
100
that is fabricated using a conventional logic process.
FIG. 1B
is a cross sectional view of DRAM cell
100
. As used herein, a conventional logic process is defined as a semiconductor fabrication process that uses only one layer of polysilicon and provides for either a single-well or twin-well structure. DRAM cell
100
consists of a p-channel MOS access transistor
1
having a gate terminal
9
connected to word line
3
, a drain terminal
17
connected to bit line
5
, and a source terminal
18
connected to the gate
11
of a p-channel MOS transistor
2
. The connection between source terminal
18
and the gate
11
undesirably increases the layout area of DRAM cell
100
. P-channel transistor
2
is configured to operate as a charge storage capacitor. The source and drain
19
of transistor
2
are commonly connected. The source, drain and channel of transistor
2
are connected to receive a fixed plate bias voltage V
pp
. The V
pp
voltage is a positive boosted voltage that is higher than the positive supply voltage V
dd
by more than a transistor threshold voltage V
t
.
As used herein, the electrode of the charge storage capacitor is defined as the node coupled to the access transistor, and the counter-electrode of the charge storage capacitor is defined as the node coupled to receive a fixed plate bias voltage. Thus, in DRAM cell
100
, the gate
11
of transistor
2
forms the electrode of the charge storage capacitor, and the channel region of transistor
2
forms the counter-electrode of the charge storage capacitor.
To improve soft-error-rate sensitivity of DRAM cell
100
, the cell is fabricated in an n-well region
14
which is located in a p-type substrate
8
. To minimize the sub-threshold leakage of access transistor
1
, n-well
14
is biased at the V
pp
voltage (at n-type contact region
21
). However, such a well bias increases the junction leakage. As a result, the bias voltage of n-well
14
is selected such that the sub-threshold leakage is reduced without significantly increasing the junction leakage. When storing charge in the storage capacitor, bit line
5
is brought to the appropriate level (i.e., V
dd
or V
SS
) and word line
3
is activated to turn on access transistor
1
. As a result, the electrode of the storage capacitor is charged. To maximize the stored charge, word line
3
is required to be driven to a negative boosted voltage V
bb
that is lower than the supply voltage V
SS
minus the absolute value of the threshold voltage (V
tp
) of access transistor
1
.
In the data retention state, access transistor
1
is turned off by driving word line
3
to the V
dd
supply voltage. To maximize the charge storage of the capacitor, the counter electrode is biased at the positive boosted voltage V
pp
. The plate voltage V
pp
is limited by the oxide breakdown voltage of the transistor
2
forming the charge storage capacitor.
DRAM cell
100
and its variations are documented in U.S. Pat. No. 5,600,598, entitled “Memory Cell and Wordline Driver For Embedded DRAM in ASIC Process,” by K. Skjaveland, R. Township, P. Gillingham (hereinafter referred to as “Skjaveland et al.”), and “A 768k Embedded DRAM for 1.244 Gb.s ATM Switch in a 0.8 um Logic Process,” P. Gillingham, B. Hold, I. Mes, C. O'Connell, P. Schofield, K. Skjaveland, R. Torrance, T. Wojcicki, H. Chow, Digest of ISSCC, 1996, pp. 262-263 (hereinafter referred to as “Gillingham et al.). Both Skjaveland et al. and Gillingham et al. describe memory cells that are contained in an n-well formed in a p-type substrate.
FIG. 2
is a schematic diagram of a word line control circuit
200
including a word line driver circuit
201
and a word line boost generator
202
described by Gillingham et al. Word line control circuit
200
includes p-channel transistors
211
-
217
, inverters
221
-
229
, NAND gates
231
-
232
and NOR gate
241
, which are connected as illustrated. Word line driver
201
includes p-channel pull up transistor
211
, which enables an associated word line to be pulled up to the V
dd
supply voltage. P-channel pull down transistors
212
-
217
are provided so that the word line can be boosted down to a negative voltage (i.e., −1.5V) substantially below the negative supply voltage V
SS
. However, the p-channel pull down transistors
212
-
217
have a drive capability much smaller (approximately half) than an NMOS transistor of similar size. As a result, the word line turn on of Gillingham et al. is relatively slow (>10 ns). Furthermore, in the data retention state, word line driver
201
only drives the word line to the V
dd
supply voltage. As a result, the sub-threshold leakage of the access transistor in the memory cells may not be adequately suppressed.
DRAM cells similar to DRAM cell
100
have also been formed using n-channel transistors fabricated in a p-type well region. To maximize stored charge in such n-channel DRAM cells during memory cell access, the associated word line is driven to a voltage higher than the supply voltage V
dd
plus the absolute value of the threshold voltage (V
tn
) of the access transistor. In the data retention state, the n-channel access transistor is turned off by driving the word line to V
SS
supply voltage (0 Volts). To maximize the charge storage of the capacitor in an n-channel DRAM cell, the counter electrode is biased at a plate voltage V
bb
that is lower than the V
SS
supply voltage.
A prior art scheme using n-channel DRAM cells includes the one described by Hashimoto et al. in “An Embedded DRAM Module using a Dual Sense Amplifier Architecture in a Logic Process”, 1997 IEEE International Solid-State Circuits Conference, pp. 64-65 and 431. A p-type substrate is used, such that the memory cells are directly in contact with the substrate and are not isolated by any well structure. In the described design, substrate bias is not permitted. Moreover, application of a negative voltage to the word line is not applicable to ASICs that restrict substrate biasing to be zero. Consequently, the architecture achieves a negative gate-to-source voltage (V
gs
) by limiting bit line swing. The negative V
gs
voltage reduces sub-threshold leakage in the memory cells. Hashimoto et al. fails to describe the structure of the word line driver.
It would therefore be desirable to have a word line driver circuit that improves the leakage currents in DRAM cells fabricated using a conventional logic process. Moreover, it would be desirable to have improved methods for biasing DRAM cells fabricated using a conventional logic process.
SUMMARY
Accordingly, the present invention provides a memory system that includes a dynamic random access memory (DRAM) cell, a word line, and a CMOS word line driver fabricated using a conventional logic process.
In another embodiment of the present invention, a DRAM cell is fabricated by slightly modifying a conventional logic process. In this embodiment, the DRAM cell is fabricated by forming the gate electrode of an access transistor from a first conductive layer, and then forming a capacitor structure. In one embodiment, the capacitor structure is fabricated by forming a crown electrode of a capacitor structure from a second conductive layer, forming a dielectric layer over the crown electrode, and then forming an plate electrode over the dielectric layer from a third conductive layer. A first set of thermal cycles are performed during the formation of the capacitor structure. After the capacitor structure has been formed, P+ and/or N+ ion implantations are performed, thereby forming shallow junctions on the chip (e.g., a drain

Affiliated with

Also associated with

Rating

DRAM cell fabricated using a modified logic process and... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM cell fabricated using a modified logic process and..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM cell fabricated using a modified logic process and... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3017029