Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-06-04
2003-07-01
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C438S243000, C257S303000
Reexamination Certificate
active
06586795
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a DRAM cell configuration, that is, to an array of memory cells with dynamic random access, and to a method for producing the configuration.
For a memory cell of a DRAM cell configuration, at present almost exclusively a so-called one-transistor memory cell is used, which includes one transistor and one capacitor. The information in the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor, so that when the transistor is triggered via a word line, the charge of the capacitor can be read out via a bit line.
The general goal is to create a DRAM cell configuration that has a high packing density.
U.S. Pat. No. 5,208,657 describes a DRAM cell configuration in which a memory cell includes a transistor and a capacitor. To increase the packing density, the transistor is disposed on four flanks of an indentation in which a memory node of the capacitor is disposed. The indentation is disposed below a region in which a word line and a bit line of the memory cell intersect. The transistor is embodied as a vertical transistor, and its gate electrode is disposed in the indentation above the memory node. The space required for the memory cell is at least 6.25 F, where F is the minimum feature size feasible in the production technology employed.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a DRAM cell configuration and a production method which overcome the above-noted deficiencies and disadvantages of the prior art devices and methods of this general kind, and whereby the invention provides for a DRAM cell configuration whose memory cells can have transistors and capacitors with improved electrical properties compared with the prior art, without having to reduce the packing density of the DRAM cell configuration. It is a further object to provide for a method for producing such a DRAM cell configuration.
With the above and other objects in view there is provided, in accordance with the invention, a DRAM cell configuration, comprising:
a substrate and memory cells each including at least one vertical transistor and one capacitor, a first indentation and a second indentation;
said first indentation and said second indentation being laterally offset from one another, with said second indentation of a first memory cell adjoining said first indentation of an adjacent, second memory cell and adjoining said substrate;
an upper source/drain region, a channel region, and a lower source/drain region of said transistor being disposed in said substrate, one above the other, and each adjoining a first flank of said first indentation and adjoining said second indentation;
a capacitor dielectric of said capacitor formed on at least a portion of said first flank of said first indentation, said dielectric having a recess formed therein in a region of said lower source/drain region of said transistor, and wherein a bottom of said second indentation is located lower than a lower edge of said recess;
said capacitor having a memory node disposed in said first indentation, and said node in said recess adjoining said lower source/drain region of said transistor;
said transistor having a gate electrode disposed in said second indentation; and
a word line connected to said gate electrode of said transistor of said memory cell, and a bit line extending transversely to said word line and connected to said upper source/drain region.
In other words, the objects of the invention are attained by a DRAM cell configuration which has memory cells that each include at least one vertical transistor and one capacitor. An upper source/drain region, a channel region, and a lower source/drain region of the transistor are disposed one above the other, and each adjoins both a first flank of the first indentation and the second indentation. At least a portion of the first flank of the first indentation is provided with a capacitor dielectric of the capacitor, which dielectric has a recess in the region of the lower source/drain region of the transistor. A memory node of the capacitor is disposed in the first indentation, and in the recess this node adjoins the lower source/drain region. A gate electrode of the transistor is disposed in the second indentation.
The memory cells are connected to word lines and to bit lines that extend transversely to the word lines.
The object is also attained by a method for producing a DRAM cell configuration, in which memory cells are created, which each have one vertical transistor and one capacitor. As parts of the transistor in the substrate, a lower source/drain region, a channel region, and an upper source/drain region are created, so that they are disposed one above the other. In the substrate, a first indentation is created, which with a first flank adjoins the lower source/drain region, the channel region, and the upper source/drain region. The first indentation is provided with a capacitor dielectric of the capacitor. The capacitor dielectric is provided with a recess on the first flank of the first indentation, in the region of the lower source/drain region. In the first indentation, a memory node of the capacitor is created, which in the recess adjoins the lower source/drain region. A second indentation is created that adjoins the upper source/drain region, the channel region, and the lower source/drain region. A gate electrode of the transistor is created in the second indentation. Word lines and bit lines, which extend transversely to the word lines, are created and connected to the memory cells.
The second indentation of the memory cell is located outside the first indentation of the memory cell.
The DRAM cell configuration can have a high packing density, since the transistor is designed as a vertical transistor, the memory node is disposed in an indentation, and a connection between the memory nodes and the lower source/drain region is made possible by means of a recess of the capacitor dielectric, which requires no additional space.
The quality of a boundary layer of the channel region, where a gate dielectric of the transistor is created, generally has a great influence on electrical properties of the transistor. It is consequently advantageous to produce this boundary layer with special care. In comparison to U.S. Pat. No. 5,208,657, the transistor can be produced with improved electrical properties, since different indentations are provided for the capacitor and for the transistor, and so the boundary layer of the channel region can remain spared from process steps for creating the first indentation.
The provision of two different indentations furthermore offers the advantage that the geometry of the boundary layer of the channel region can be independent of any geometry of a face at which the capacitor dielectric is created. The boundary layer of the channel region is preferably flat, so that it has a defined orientation with regard to the crystal lattice of the substrate, so that the gate dielectric can grow homogeneously. The face in which the capacitor dielectric is created is conversely preferably curved, so that the capacitor dielectric has no edges where field distortions could lead to leakage currents. Both the transistor and the capacitor can have especially good electrical properties.
A horizontal cross section through the first indentation is circular or elliptical, for instance.
To increase the packing density, it is advantageous if the first indentations and the second indentations of the memory cells are disposed such that the second indentation of a first one of the memory cells adjoins the memory node which is disposed in the first indentation of a second one of the memory cells. The memory cells are immediately adjacent one another or overlap.
To simplify the process, it is advantageous if the memory node is created at least at first such that at least also at a second flank of the first indentation, which flank is opposite the first flank of the first indentation, in the region of a further recess, it a
Bertagnolli Emmerich
Goebel Bernd
Fahmy Wael
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Pham Hoai V.
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