Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Patent
1998-06-08
2000-07-11
Hardy, David
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
257306, 257330, H01L 27108
Patent
active
060876921
ABSTRACT:
A DRAM cell, including memory cells each having a first transistor, a second transistor and a third transistor. The memory cells also have a writing bit line, a writing word line, a read-out word line and a read-out bit line. The first transistor has a gate electrode and a second source/drain region. The second transistor has a gate electrode, a first source/drain region, and a second source/drain region. The gate electrode of the first transistor is connected to the first source/drain region of the second transistor. The second source/drain region of the second transistor is connected to said writing bit line. The gate electrode of the second transistor is connected to the writing word line. The third transistor has a gate electrode, a first source/drain region, and a second source/drain region. The gate electrode of the third transistor is connected to the read-out word line. The second source/drain region of the first transistor is connected to the first source/drain region of the third transistor. The second source/drain region of the third transistor is connected to the read-out bit line. The first, second and third transistors are vertical MOS transistors. The invention also teaches the process steps for fabricating the DRAM cell.
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Bertagnolli Emmerich
Gobel Bernd
Greenberg Laurence A.
Hardy David
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
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