Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-12
2003-01-07
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C257S296000, C257S306000, C257S303000, C257S311000, C257S300000, C438S270000, C438S268000, C438S259000, C438S243000, C438S249000, C438S241000, C365S145000, C365S182000, C365S207000
Reexamination Certificate
active
06504200
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a DRAM cell configuration, i.e. a dynamic random access memory cell configuration, in which bit lines are buried in a substrate, and to a method of fabricating the DRAM cell configuration.
At present, DRAM cell configurations are formed with memory cells that are almost exclusively so-called one-transistor memory cells. Those cells each comprise one transistor and one capacitor. The information of the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor, with the result that when the transistor is driven via a word line, the charge of the capacitor can be read out via a bit line.
It is generally endeavored to produce a DRAM cell configuration with high packing density.
U.S. Pat. No. 5,497,017 describes a DRAM cell configuration comprising one-transistor memory cells. A space requirement per memory cell may be 4F
2
, where F is the minimum feature size that can be fabricated in the technology used. In order to produce bit lines, trenches running parallel to one another are etched in a silicon substrate. A thin insulating layer is deposited which does not fill the trenches. In order to produce the bit lines, the trenches are filled with tungsten. The insulating layer is in each case removed from a side wall of each trench, with the result that the bit lines are partly uncovered laterally. Source/drain regions and channel regions of vertical transistors are produced by epitaxy. In this case, lower source/drain regions of the transistors laterally adjoin the bit lines. Word lines run transversely with respect to the bit lines and in trenches, which are arranged between mutually adjacent transistors.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a DRAM cell configuration whose memory cells each have a transistor and a capacitor, which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and the bit lines of which are buried in the substrate and which can be fabricated with a space requirement per memory cell of 4F
2
and, at the same time, with lower process complexity by comparison with the prior art. Furthermore, it is an object of the invention to provide a fabrication method for producing the novel DRAM cell configuration.
With the foregoing and other objects in view there is provided, in accordance with the invention, a DRAM cell configuration, comprising:
a plurality of memory cells each having a vertical transistor and a capacitor;
a substrate formed with substantially parallel trenches each having side walls and having a bit line arranged therein in a lower part thereof;
an insulation formed in the lower part of a respective said trench between said bit line and said substrate, except for a strip-type cut-out formed parallel to said trench and in said first sidewall of said trench;
a further insulation formed on parts of said side walls of said trench above the lower part of said trench and an upper area of said bit line;
word lines extending transversely with respect to said bit line, said word lines, except for downwardly directed protuberances that reach into said trenches and that are arranged above said bit lines, running above said substrate, and an insulating layer isolating said word lines from said substrate;
said protuberances of said word lines and insulating structures being arranged alternately above said bit line in said trench;
said transistors having upper source/drain regions and lower source/drain regions arranged between said trenches and under said word lines;
further insulating structures formed in said substrate for insulating from one another upper source/drain regions of mutually adjacent transistors along said trench; and
wherein said upper source/drain regions of said transistors are connected to said capacitors of said memory cells.
In other words, the problems underlying the invention are solved by means of a DRAM cell configuration having memory cells which each have a transistor and a capacitor, in which a substrate has trenches which essentially run parallel to one another and in each of which a bit line is arranged. The bit line is arranged in a lower part of the associated trench. The lower part of the trench, except for a strip-type cut-out which runs parallel to the trench and is arranged on a first side wall of the trench, is provided with an insulation, which is arranged between the bit line and the substrate. Parts of the side walls of the trench which are arranged above the lower part of the trench and an upper area of the bit line are provided with a further insulation. Word lines run transversely with respect to the bit line. The word lines, except for downwardly directed protuberances, which reach into the trenches and are arranged above the bit lines, run above the substrate. Insulating structures and the protuberances of the word lines are arranged alternately in the trench above the bit lines. The transistors of the memory cells are configured as vertical transistors. Upper source/drain regions and lower source/drain regions of the transistors are arranged between the trenches. Further insulating structures are arranged in the substrate, which structures isolate from one another upper source/drain regions of mutually adjacent transistors along the trench. The upper source/drain regions of the transistors are connected to the capacitors of the memory cells.
The protuberances of the word lines act as gate electrodes of the transistors.
With the above and other objects in view there is also provided, in accordance with the invention, a method of fabricating a DRAM cell configuration. The method comprises the following method steps:
producing an insulating layer on a substrate;
forming substantially parallel trenches in the substrate;
providing an insulation for lower parts of the trenches, except for strip-type cut-outs running parallel to the trenches and arranged on first side walls of the trenches;
producing a bit line in each trench in a lower part thereof;
providing a further insulation for parts of the side walls of the trenches arranged above the lower parts of the trenches and for the bit lines;
filling the trenches with a conductive material;
covering the conductive material with a protective layer;
patterning the conductive material and the protective layer to produce word lines covered by the protective layer and running transversely with respect to the bit lines and having downwardly directed protuberances reaching into the trenches;
depositing insulating material and etching the insulating material back together with the insulating layer selectively with respect to the protective layer and with respect to the substrate, until the substrate is uncovered, such that insulating structures are produced in the trenches, between the protuberances of the word lines and above the bit lines;
etching the substrate selectively with respect to the insulating structures to produce depressions between the word lines and between the trenches;
producing upper source/drain regions of transistors of memory cells between the trenches and between the depressions in the substrate;
producing lower source/drain regions of the transistors each adjoining one of the cut-outs, in the substrate under the upper source/drain regions;
producing further insulating structures in the depressions; and
producing capacitors of the memory cells and connecting each of the capacitors to one of the upper source/drain regions.
In other words, the problems underlying the invention are furthermore solved by means of a method for fabricating a DRAM cell configuration having memory cells which each have a transistor and a capacitor, in which an insulating layer is produced on a substrate. Trenches, which essentially run parallel to one another are produced in the substrate. Lower parts of the trenches, except for strip-type cut-outs which run parallel to the trenches and are arranged on first side walls of the trenches, are provided with an insul
Schlösser Till
Sell Bernhard
Willer Josef
Erdem Fazli
Flynn Nathan J.
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
LandOfFree
DRAM cell configuration and fabrication method does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with DRAM cell configuration and fabrication method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM cell configuration and fabrication method will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3057013