Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-10-19
2002-03-26
Ho, Hoai V. (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S315000, C365S185080, C365S149000
Reexamination Certificate
active
06362502
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a DRAM cell circuit, that is to say a dynamic random access memory cell circuit.
At the present time, a so-called one-transistor memory cell is usually used as the memory cell of the DRAM cell circuit. Such a memory cell contains a transistor and a capacitor on which the information is stored in the form of a charge. By driving the transistor via a word line, the charge on the capacitor can be read out via a bit line. Since the charge of the capacitor drives the bit line and a signal generated by the charge should remain identifiable despite background noise, the capacitor must have a minimum capacitance. In order to attain the highest possible packing density of the DRAM cell circuit, capacitors are proposed which have surfaces of a complicated configuration or which have capacitor dielectrics made of special materials having high dielectric constants.
An alternative DRAM cell circuit avoids the high process outlay for producing capacitors with a small space requirement and a large capacitance. The reference by M. Heshami et al. “250-MHz Skewed-Clock Pipelined Date Buffer”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 3, March 1996, 376, describes a DRAM cell circuit in which a memory cell is a dynamic gain memory cell which contains a first selection transistor, a memory transistor and a second selection transistor. The first selection transistor is connected between a first bit line and a gate electrode of the memory transistor. A gate electrode of the first selection transistor is connected to a first word line. The second selection transistor is connected between a source/drain region of the memory transistor and a second bit line. A gate electrode of the second selection transistor is connected to a second word line. A further source/drain region of the memory transistor is connected to a voltage terminal. As in the case of the one-transistor memory cell, the information is stored in the form of an electric charge. However, the electric charge does not have to drive the bit line directly, but rather is stored on the gate electrode of the memory transistor and serves only for controlling the latter, for which purpose even a very small quantity of electric charge is sufficient. In order to write an item of information to the gate electrode of the memory transistor, the first selection transistor is driven via the first word line, with the result that there is established at the gate electrode of the memory transistor a voltage which is dependent on a voltage on the first bit line, the magnitude of which in turn depends on the information to be written. In order to read out the information, the second selection transistor is driven via the second word line. Depending on the information, that is to say depending on the voltage on the gate electrode of the memory transistor, the memory transistor is in the on state or in the off state, and a current does or does not flow between the voltage terminal and the second bit line.
An EPROM is a nonvolatile memory cell circuit in which, in contrast to the DRAM cell circuit, the information does not have to be continuously refreshed again. The information is stored in the form of at least two different threshold voltages of transistors. In order to read out an item of information of one of the transistors, a voltage lying between the two threshold voltages is applied to a control gate electrode of the transistor. Depending on whether or not a current flows through the transistor, the logic value zero or one is read out. The threshold voltage of the transistor can be set by a floating gate electrode that is electrically insulated and disposed between the control gate electrode and a channel region of the transistor. To that end, a voltage drop is produced between the control gate electrode and the channel region or a source/drain region of the transistor, which causes electrons to tunnel into the or from the floating gate electrode. Different charges of the floating gate electrode lead to different threshold voltages of the transistor. Since the floating gate electrode is completely insulated, there are no leakage currents and the information does not have to be refreshed again.
The literature reference IEEE Transactions on Electron Devices, Volume 41, No. 6, June 1994, pages 926 to 930 describes a DRAM cell circuit having a p-channel writing transistor and an n-channel reading transistor which has a floating gate. The control gate electrodes of both transistors are connected to a word line. One of the source/drain terminals of the reading transistor is at a supply potential, and the other of its source/drain terminals is connected to a bit line. One of the source/drain terminals of the writing transistor is connected to the floating gate of the reading transistor, and the other is connected to the bit line.
U.S. Pat. No. 5,220,530 teaches a memory cell having an access transistor, whose gate electrode is connected to a word line, and a further transistor with a floating gate. One of the source/drain terminals of the access transistor is connected to a bit line, and the other source/drain terminal is connected to the control gate electrode of the further transistor. One of the source/drain terminals of the further transistor is connected to the bit line, and the other is connected to a supply potential.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a DRAM cell circuit and a method for fabricating it that overcomes the above-mentioned disadvantages of the prior art methods and devices of this general type, which can be fabricated with a low process outlay in conjunction with a high packing density. Furthermore, the intention is to specify a method for operating the DRAM cell circuit and a method for producing the DRAM cell circuit.
With the foregoing and other objects in view there is provided, in accordance with the invention, a dynamic random access memory (DRAM) cell circuit, which includes a voltage terminal, a word line, a bit line running transversely to the word line, and a plurality of memory cells. Each of the memory cells contains a memory transistor having a channel region, a control gate electrode, a floating gate electrode, a first source/drain region, and a second source drain region. A transfer transistor having a gate electrode, a first source/drain region and a second source/drain region is also part of each of the memory cells. The word line is connected to the gate electrode of the transfer transistor. A first dielectric layer is disposed between and isolates the floating gate electrode of the memory transistor from the channel region of the memory transistor, and the floating gate electrode is connected to the first source/drain region of the transfer transistor. A second dielectric layer is disposed between and isolates the control gate electrode of the memory transistor from the floating gate electrode of the memory transistor, and the control gate electrode is connected to the word line. The first source/drain region of the memory transistor is connected to the bit line, and the second source/drain region of the memory transistor and the second source/drain region of the transfer transistor are connected to the voltage terminal.
The problem is solved by a DRAM cell circuit having a plurality of memory cells, in which the memory cells each have a memory transistor and a transfer transistor. The gate electrode of the transfer transistor is connected to the word line. The memory transistor has a floating gate electrode that is isolated from the channel region of the memory transistor by the first dielectric layer and is connected to the first source/drain region of the transfer transistor. The memory transistor has a control gate electrode, which is isolated from the floating gate electrode by the second dielectric layer and is connected to the word line. The first source/drain region of the memory transistor is connected to the bit line, which runs transversely with respect to the word line. The seco
Hofmann Franz
Risch Lothar
Rösner Wolfgang
Schulz Thomas
Greenberg Laurence A.
Ho Hoai V.
Infineon - Technologies AG
Lerner Herbert L.
Stemer Werner H.
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