Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-08-27
2001-01-09
Jackson, Jr., Jerome (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S302000, C257S398000, C257S399000
Reexamination Certificate
active
06172391
ABSTRACT:
BACKGROUND OF THE INVENTION
What are referred to as single transistor memory cells are almost exclusively utilized in DRAM cell arrangements, i.e. memory cell arrangements with dynamic, random access. A single-transistor memory cell has a selection transistor and a storage capacitor. The information in the form of an electrical charge is stored in the storage capacitor, this representing a logical quantity, 0 or 1. This information can be read out via a bit line by driving the selection transistor via a word line.
Since the storage density increases from memory generation to memory generation, the required area of the single-transistor memory cell must be reduced from generation to generation. Since the reduction of the structural sizes has limits placed upon it by the minimum structural size F manufacturable in the respective technology, this also involves a modification of the single transistor memory cell. Up to the 1MBit generation, thus, both the selection transistor as well as the storage capacitor were realized as planar components. Beginning with the 4MBit memory generation, a further reduction in area had to ensue on the basis of a three-dimensional arrangement of selection transistor and storage capacitory.
One possibility is realizing the storage capacitor not in planar fashion but in a trench (see, for example, K. Yamada et al., “A Deep Trenched Capacitor Technology For 4MBit DRAMs”, Proc. Intem. Electronic Devices and Materials IEDM 85, page 702).
Another possibility is employing vertical MOS transistors as disclosed, for example, in U.S. Pat. No. 5,376,575.
The earlier German Patent Application 196 20 625.1 discloses a DRAM cell arrangement whose selection transistors are fashioned as vertical MOS transistors above storage capacitors. To that end, first trenches and second trenches transverse thereto are generated in a substrate. The storage capacitors are respectively arranged in the trenches. Respectively two of the second trenches form a trench pair that is surrounded by an insulation structure. A semiconductor island is arranged between the second trenches of each trench pair. A first selection transistor with a first gate electrode is arranged at a first, common sidewall of the semiconductor island and of a first of the two second trenches, and a second transistor with a second gate electrode is arranged at a second, common sidewall of the semiconductor island and of a second of the two second trenches. A respective storage node of the storage capacitors is adjacent at one of the sidewalls of the semiconductor island. In order to enable folded bit lines, the semiconductor islands are respectively arranged offset relative to one another along neighboring, first trenches. Given folded bit lines, the signal of the appertaining bit line is compared to the signal of a neighboring bit line for reading of the information of the selection transistor. The word line via which the selection transistor is driven cannot be connected to any selection transistor that is connected to the neighboring bit line. Disturbances and signal background that are the same on the bit lines lying extremely close to one another can thereby be nearly eliminated. This is advantageous, since the signal that must be interpreted as the bit line becomes smaller and smaller with the reduction of the structural size.
German reference DE 195 191 60 C1 discloses a DRAM cell arrangement that has a vertical MOS transistor per memory cell whose first source/drain region is connected to a storage node of a storage capacitor whose channel region is annularly surrounded by a gate electrode and whose second source/drain region is connected to a bearing bit line. The storage capacitor is either a planar capacitor or a stacked capacitor.
U.S. Pat. No. 4,630,088 discloses a DRAM cell arrangement wherein a capacitor of a memory cell is connected between a selection transistor of the memory cell and a bit line. A word line is arranged at each of two opposite sidewalls of a strip-shaped semiconductor structure. The semiconductor structure comprises an upper and a lower source/drain region of the selection transistor. A channel region is arranged between the source/drain regions. The upper source/drain region is adjacent at one of the two sidewalls. A doped region that is doped of the same conductivity type as that of the channel region but exhibits a higher dopant concentration is arranged next to the upper source/drain region. The doped region effects that the read-out transistor is only driven by the word line that is arranged at the sidewall of the semiconductor structure which is adjoined by the upper source/drain region.
U.S. Pat. No. 5,214,603 disdoses a DRAM cell arrangement wherein a selection transistor of a memory cell is connected between a capacitor of the memory cell and a bit line. Word lines are arranged at sidewalls of trenches that proceed parallel to one another. A semiconductor structure is arranged between two of the trenches and comprises a source/drain region shared by the two selection transistors and two lower source/drain regions of the selection transistors. A doped region that is doped of a conductivity type opposite the conductivity type of the source/drain regions is arranged between the upper and the lower source/drain regions. Insulating structures that are arranged between the trenches are arranged between neighboring semiconductor structures that are parallel or perpendicular to the trenches.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a DRAM cell arrangement that has single-transistor memory cells as memory cells and that can be manufactured with especially high packing density. Further, the present invention is also a manufacturing method for such a DRAM cell arrangement.
In an inventive DRAM cell arrangement, memory cells respectively have a semiconductor structure that has at least one of two source/drain regions and a channel region of a vertical selection transistor arranged therebelow. The selection transistor is fashioned as an MOS transistor. The semiconductor structure has two sidewalls lying opposite one another at which the source/drain region is adjacent. The channel region is adjacent to one of the two sidewalls of the semiconductor structure. A gate dielectric adjoins the channel region, a gate electrode that is connected to a first word line adjoining the gate dielectric. An element that prevents the formation of a channel is arranged at another of the two sidewalls of the semiconductor structure at a level of the channel region. A second word line is adjacent at the element that prevents the formation of a channel. The element is arranged under the source/drain region, so that the DRAM cell arrangement exhibits a higher packing density then the DRAM cell arrangement according to U.S. Pat. No. 4,630,088. A first source/drain region of the selection transistor is connected to a storage capacitor. A second source/drain region of the selection transistor is connected to a bit line that proceeds transverse to the first word line. A memory cell of the DRAM cell arrangement can be manufactured with an area of 4F
2
.
The element that prevents the formation of a channel can be fashioned as a channel stop zone. The channel stop zone is doped with the same conductivity type as the channel region but exhibits a higher dopant concentration. Second trenches that separate semiconductor structures from one another can be generated for generating the channel stop zones. The channel stop zones arise by oblique implantation at first sidewalls and/or at second sidewalls of the second trenches. Channel stop zones can also arise by drive-out of dopant of an auxiliary material that is in turn subsequently removed. Alternatively, the elements can be generated in the form of spacers of insulating material at the first sidewalls and/or at the second sidewalls of the second trenches.
It is advantageous to fashion the DRAM cell arrangement with folded bit lines. To that end, respectively two word lines are generated along the second trenches. Elements tha
Bertagnolli Emmerich
Goebel Bernd
Klose Helmut
Jackson, Jr. Jerome
Schiff & Hardin & Waite
Siemens Aktiengesellschaft
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