DRAM cell arrangement and method for its production

Details DRAM cell arrangement and method for its production DRAM cell arrangement and method for its production

1999-01-12

2000-11-14

Hardy, David

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257309, H01L 27108

Patent

active

061473766

ABSTRACT:
A memory cell contains at least one transistor and one capacitor connected to an upper bit line. The capacitor contains a first capacitor electrode arranged above the transistor, and is connected to the transistor. The upper bit line can be created in self-adjusted fashion on the basis of trenches which are of different widths, which extend transversely to one another, and which are arranged between the first capacitor electrodes. At least a part of each first capacitor electrode can be created from a layer which is structured by the trenches. Trenches can be narrowed by spacers.

REFERENCES:
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4974060 (1990-11-01), Ogasawara
patent: 5055898 (1991-10-01), Beilstein, Jr. et al.
patent: 5270561 (1993-12-01), Jun
patent: 5621606 (1997-04-01), Hwang
A 250m V Bit-Line Swing Scheme for a 1V 4Gb DRAM--Inaba et al--ULSI Research Laboratories, 1995 Symposium on VLSI Circuits Digest.
Giga-bit Scale DRAM Cell with New Simple Ru/(Ba,Sr)TiO3/Ru Stacked Capacitors Using X-ray Lithography--Nishioka et al--IEDM 95-903.

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