DRAM cell arrangement and method for its production

Details DRAM cell arrangement and method for its production DRAM cell arrangement and method for its production

1999-03-23

2000-03-28

Le, Vu A.

Static information storage and retrieval

Systems using particular element

Capacitors

257302, 257906, H01L 2704

Patent

active

060440090

ABSTRACT:
A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F.sup.2, F being the minimal structural size that can be produced in the respective technology.

REFERENCES:
patent: 4462040 (1984-07-01), Ho et al.
patent: 4630088 (1986-12-01), Ogura et al.
Sze, S.M. Semiconductor Devices, AT & T Bell Laboratories, Figure 18a, p. 487.
K. Yamada et al., "A Deep-Trenched Capacitor Technology for 4 MEGA Bit Dynamic RAM", Proc. Intern. Electronic Devices and Materials, IEDM 85, pp. 702-705.

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