DRAM cell arrangement and method for its manufacture

Details DRAM cell arrangement and method for its manufacture DRAM cell arrangement and method for its manufacture

1996-05-14

1998-04-07

Meier, Stephen

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257305, H01L 27108, H01L 2976, H01L 2994, H01L 31119

Patent

active

057367612

ABSTRACT:
The DRAM cell arrangement has one vertical MOS transistor per memory cell, whose first source/drain region adjoins a trenched bitline (5), whose gate electrode (13) is connected with a trenched wordline and whose second source/drain region (3) adjoins a substrate main surface (1). A capacitor dielectric (16), which is in particular a ferroelectric or paraelectric layer, is arranged on at least the second source/drain region and a capacitor plate (17) is arranged on the dielectric, so that the second source/drain region (3) acts additionally as a memory node. The DRAM cell arrangement can be manufactured with a memory cell surface of 4 F.sup.2.

REFERENCES:
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4974060 (1990-11-01), Ogasawara
patent: 5376575 (1994-12-01), Kim et al.
Patent Abstracts of Japan, vol. 17, No. 401 (E-1404), 27 Jul. 1993, & JP-A-05 075059 (Mitsubishi Electric Corp.), 26 Mar. 1993.
Patent Abstracts of Japan, vol. 14, No. 156, (E-908), 26 Mar. 1990, & JP-A-02 014563 (Matsushita Electron Corp.), 18 Jan. 1990.
International Electron Devices Meeting, 1991, vol. 17, No. 2.1.8, 11 Dec. 1991, A Surrounding Isolation-Merged Plate electrode (Simple) Cell with checkered layout for 256M bit DRAM and beyond, T. Ozaki et al, pp. 469-472.
Patent Abstracts of Japan, vol. 16, No. 59, (E-1166), 14 Feb. 1992, & JP-A-03 256358, (Hitachi Ltd.), 15 Nov. 1991.
IEDM 85, A Deep-Trenched Capacitor Technology for 4 Mega Bit Dynamic RAM, K. Yamada, et al, pp. 702-705.
1990 Symposium on VLSI Technology, Bit-Line Shielded Memory Cell Technology for 64Mb DRAMs, Y. Kawamoto et al, pp. 13-14.

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