DRAM cell arrangement and method for its fabrication

Details DRAM cell arrangement and method for its fabrication DRAM cell arrangement and method for its fabrication

1998-06-26

2000-06-13

Tran, Minh Loan

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257300, 257302, 257303, 257309, H01L 27108

Patent

active

060752653

ABSTRACT:
The DRAM cell arrangement has three transistors per memory cell, at least one of which transistors is designed as a vertical transistor. The transistors may be formed on sidewalls (1F1, 1F2, 2F2) of trenches (G1, G2). In order to fabricate contact regions (K) which respectively connect together three source/drain regions (1 S/D1, 3 S/D2, 2 S/D 2) of different transistors, it is advantageous to arrange the trenches (G1, G2) alternately with a larger distance and a smaller distance from one another. Gate electrodes (Ga1, Ga3) of transistors may be formed as parts of writing word lines (WS) or read-out word lines (WA) in the form of spacers on sidewalls (1F1, 1F2) of the trenches (G1). Connections between gate electrodes (Ga2) and source/drain regions (3 S/D1) may be made via conductive structures (L).

REFERENCES:
patent: 5463234 (1995-10-01), Toriumi et al.
W. H. Krautschneider et al, "Fully Scalable Gain Memory Cell For Future Drams", Microelectronic Engineering 15, 1991, pp. 367-370.
K. Horninger, Integrierte MOS-Schaltungen, Springer Verlag, 1987, pp. 226-229.

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