DRAM cell arrangement and method for fabricating it

Details DRAM cell arrangement and method for fabricating it DRAM cell arrangement and method for fabricating it

2000-09-12

2002-02-19

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Interconnection arrangements

C365S149000, C257S301000

Reexamination Certificate

active

06349052

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a DRAM cell arrangement, that is to say a dynamic random access memory cell arrangement, and a method for fabricating it.
BACKGROUND OF THE INVENTION
At the present time it is almost exclusively the case that a so-called 1-transistor memory cell comprising one transistor and one capacitor is used as the memory cell of a DRAM cell arrangement. The information of the memory cell is stored in the form of a charge on the capacitor. The capacitor is connected to the transistor in such a way that when the transistor is driven via a word line, the charge of the capacitor can be read out via a bit line.
Such a DRAM cell arrangement is described e.g. in EP 0852396 A2. A storage node of the capacitor and, above it, a gate electrode of the transistor, said gate electrode being isolated from the capacitor, are arranged in a depression in a substrate. In an upper region of the storage node, the storage node directly adjoins the substrate where a source/drain region of the transistor is arranged. A further source/drain region of the transistor is arranged at a surface of the substrate, with the result that the transistor is configured as a vertical transistor. Apart from the region in which the storage node adjoins the source/drain region of the transistor, in an upper region the storage node is isolated from the substrate by a so-called collar. In remaining regions the storage node is isolated from the substrate by a capacitor dielectric. A heavily doped region which adjoins the capacitor dielectric and serves as a capacitor plate of the capacitor is arranged in the substrate. This region is produced by diffusion of dopants into the substrate, said dopants being introduced into the depression before the storage node is produced.
U.S. Pat. No. 5,902,118 describes a three-dimensional circuit arrangement produced by two substrates being stacked one on top of the other and connected, said substrates having components in the region of their interfaces which meet one another. One of the substrates is subsequently thinned from the rear side, the other substrate acting as a stabilizing support plate.
SUMMARY OF THE INVENTION
The invention is based on the problem of specifying a DRAM cell arrangement in which transistors of memory cells can have fewer leakage currents in comparison with the prior art in conjunction with a high packing density of the DRAM cell arrangement. Furthermore, the intention is to specify a method for fabricating such a DRAM cell arrangement.
The problem is solved by means of a DRAM cell arrangement having memory cells each comprising a transistor and a capacitor. A first substrate has one depression per memory cell. Areas of the depression are provided with a capacitor dielectric of the capacitor of the memory cell. The depression is filled with a storage node of the capacitor. The transistor of the memory cell is arranged in a second substrate. A first source/drain region of the transistor adjoins at least a first surface of the second substrate. A second source/drain region of the transistor adjoins at least a second surface, opposite to the first surface, of the second substrate. The first substrate and the second substrate are connected to one another in such a way that an insulating layer is arranged between them, which insulating layer adjoins the storage node and the second surface of the second substrate. The second substrate has first trenches, which isolate source/drain regions of mutually adjacent transistors from one another and which each cut through the second substrate and the insulating layer. At least one contact is arranged in the insulating layer, which contact adjoins one of the first trenches, the second source/drain region and the storage node. Bit lines and word lines running transversely with respect thereto are provided, which are connected to the memory cells.
The problem is furthermore solved by means of a method for fabricating a DRAM cell arrangement, in which a plurality of memory cells are produced. One depression is produced per memory cell in a first substrate. Areas of the depression are provided with a capacitor dielectric of a capacitor of the memory cell. The depression is filled with a storage node of the capacitor. The first substrate is connected to the second substrate, an insulating layer being produced which is arranged between said substrates and adjoins the storage node and the second substrate. The second substrate is thinned from a first surface, the first surface being opposite to a second surface, adjoining the insulating layer, of the second substrate. A first source/drain region of a transistor of the memory cell is produced in such a way that it adjoins at least the first surface of the second substrate. First trenches are produced in the second substrate, which trenches each cut through the second substrate and the insulating layer, parts of the insulating layer which adjoin the first trenches also adjoining the storage nodes of the capacitors of the memory cells. A second source/drain region of the transistor is produced in such a way that it adjoins at least one of the first trenches and at least one of the parts of the insulating layer. The parts of the insulating layer are removed by isotropic etching. The parts of the insulating layer are replaced by contacts by conductive material being deposited and etched back. Bit lines and word lines running transversely with respect thereto are produced and are connected to the memory cells.
The first trenches cut through the insulating layer in order that the parts of the insulating layer which are arranged underneath the second source/drain regions can be removed during the isotropic etching.
During the thinning of the second substrate, the first substrate acts as a stabilizing support plate.
The DRAM cell arrangement can have a high packing density since the transistor is arranged above the capacitor and the contact does not require any additional space but rather is arranged below the transistor. The first trenches, which serve for isolating the source/drain regions of the mutually adjacent transistors, are also used for producing the contacts between the transistors and the capacitors. The isotropic etching enables the contacts to be produced in a laterally offset manner with respect to the first trenches, so that they are arranged underneath the second source/drain regions.
Since the transistor and the capacitor are produced in different substrates, the production of the depression, which is generally effected by anisotropic etching, does not have any adverse effects on the transistor, with the result that the latter can have fewer leakage currents. By way of example, defects which can arise during the production of the depressions in the first substrate do not impair the transistors since the transistors are produced in a different, the second, substrate. The process steps for producing the capacitor can be optimized without having to consider the transistor. The transistors also do not have to be considered when choosing the material for a mask for producing the depressions. By way of example, the mask may be produced from metal.
Since the storage node does not adjoin the first substrate, the complicated production of a collar can be dispensed with. It suffices for all areas of the depression to be provided with the capacitor dielectric.
Since only the capacitors but not the transistors of the DRAM cell arrangement are arranged in the first substrate, a capacitor electrode of the capacitors can be produced in a manner other than by diffusion of dopant into the first substrate, said dopant being introduced into the depression. By way of example, the entire first substrate may be composed of heavily doped monocrystalline silicon or polysilicon and form the capacitor electrode. This means a significant reduction in the process complexity.
A particularly high packing density can be obtained if the transistor is configured as a vertical transistor. To that end, the second source/drain region is arranged below the first source/

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