DRAM cell arrangement

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257300, 257301, 257906, 257907, H01L 2976

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active

060970499

ABSTRACT:
A DRAM cell arrangement and method for manufacturing same, wherein a storage capacitor is connected via a first source/drain zone of a vertical selection transistor and a bit line. Since the storage capacitor and the bit line are arranged substantially above a substrate, the bit line can be manufactured of materials having high electrical conductivity, and materials having a high dielectric constant can be utilized for the storage capacitor. At least the first source/drain zone and a channel zone are parts of a projection-like semiconductor structure that is laterally limited by at least two sidewalls. A respective word line can be arranged at the two sidewalls. An element that prevents the drive of the selection transistor by this word line is arranged between the channel zone and one of the word lines. A second source/drain zone of the selection transistor is buried in the substrate and, for example, is part of a doped layer or of a grid-shaped doped region or is connected to the substrate via a buried contact. A memory cell can be manufactured given open bit lines as well as given folded bit lines, wherein it is manufactured with an area of 4F.sup.2.

REFERENCES:
patent: 4630088 (1986-12-01), Ogura et al.
patent: 4737829 (1988-04-01), Morimoto et al.
patent: 4949138 (1990-08-01), Nishimura
patent: 5307310 (1994-04-01), Narita
patent: 5977589 (1999-11-01), Schloesser
Semiconductor devices, physics and technology, p. 487.
A Deep-Trenched Capacitor Technology for 4 MEGA Bit Dynamic Ram, E. Yamada et al., pp. 702-705.
Patent Abstracts of Japan--03131064--Apr. 6, 1991.

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