Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-02-25
2001-02-06
Chaudhuri, Olik (Department: 2823)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S303000, C257S306000
Reexamination Certificate
active
06184548
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the dynamic random access memories (DRAM) and more particularly to the structures and methods of fabrication of DRAM's storing multiple data bits per DRAM cell.
2. Description of Related Art
The fabrication and structure of DRAM cells and DRAM arrays are well known in the art. Typical cell structures for high density DRAM in prior art is composed of one transistor M
1
70
for switching charges and one storage capacitor C
65
for storing charges is illustrated in
FIGS. 1
a
and
1
c.
The transistor M
1
70
will be an n-MOS transistor fabricated as shown in
FIGS. 1
b
and
1
c.
A deep N-well
10
will be formed in a p-type substrate
5
. The area for DRAM cells will be formed as openings during the formation of insulation. The insulation is formed by the local oxidation of the silicon substrate (LOCOS)
20
. Within the deep n-well
10
a shallower p-well
15
will be formed. The gate
40
of the n-MOS transistor M
1
70
will be formed as a conductive material such as polysilicon placed over an insulating gate oxide
35
to define the channel area that will be between the drain
30
and source
25
of the n-MOS transistor M
1
70
.
The drain
30
and the source
25
will be formed by masking the semiconductor substrate
5
and implanting an N
+
material to form the N
+
drain
30
and the N
+
source
25
. The gate
40
of the MOS transistor M
1
70
will be connected to the word line control circuitry (not shown).
The capacitor C
25
is formed by placing a conductive metal connected to the substrate biasing voltage source V
ss
on a dielectric placed over the N
+
drain of the transistor M
1
70
. The capacitor C
25
as shown is diagrammatic. The particular structure of the capacitor C
25
is well known and shown in “The Evolution Of DRAM Cell Technology” by B. El-Kareh et al., Solid State Technology, May 1997, pp. 89-101. In order to maintain the minimum storage capacitance of 30-40 fF of a cell, the structure of the DRAM cell results in complex semiconductor processing to develop these structures.
Refer now to
FIGS. 1
c
and
1
d,
The trench capacitor C
T
165
is formed by etching a deep trench
167
in the surface of the semiconductor substrate
105
. An N
+
material is implanted in the surface of the trench
167
and to the N
+
drain
130
to form an N
+
strap
152
. An insulating material such as oxidized silicon nitride ONO, silicon dioxide, or silicon nitride will then be deposited on the surface of the trench
167
to form the capacitor dielectric
155
. A conductive material such as polysilicon will be deposited in the trench
167
to fill the trench
167
. The polysilicon “plug”
160
will then be attached to the substrate biasing voltage source V
ss
175
to form a bottom plate of the capacitor C
T
165
. The top plate of the capacitor C
T
165
will be the N
+
diffusion
150
that is connected by the N
+
strap
152
to the N
+
drain
130
of the MOS transistor M
1
170
. Again
FIG. 1
d
is diagrammatic. The particular structure is well known in the art and illustrated in B. El-Kareh et al.
The deep n-well
110
is typically biased to the power supply voltage source V
cc
(i.e. the highest potential on chip) and the p-well is biased to substrate biasing voltage source V
ss
175
(i.e. the lowest voltage on chip). The substrate biasing voltage source V
ss
175
may be biased below ground (i.e. negative potential) so that the leakage current through the pass transistor is reduced. The presence of charge in the storage capacitor C
165
indicates a logical “1” and its absence of charge indicates a logical “0”. The storage capacitor C
165
is connected to N
+
drain
130
of the transistor M
1
170
, and the other N
+
source
125
of the transistor M
1
170
is connected to bit-line V
bit
180
that controls the reading and writing of the DRAM cell. The gate
140
of the MOS transistor M
1
170
is connected to the word line V
word
185
to control the selection of the DRAM cell.
U.S. Pat. No. 4,896,197 (Mashiko) describes a DRAM cell incorporating a trench capacitor to store one bit and a stack capacitor to store a second bit. A first pass transistor controls the charge of the trench capacitor, while a second pass transistor controls the charge of the stacked capacitor. The trench capacitor and the stack capacitor have a common L shaped plate between them. The L shaped common plate would be coupled to the substrate biasing voltage source V
ss
of
FIGS. 1
a
and
1
c.
U.S. Pat. No. 5,066,608 (Kim et al.) describes a method for manufacture of a stacked-trench capacitor. The stacked-trench capacitor will incorporate both a trench capacitor and stack capacitor to increase the capacitance of the DRAM cell.
U.S. Pat. No. 5,217,918 (Kim et al.) discloses an integrated semiconductor memory device incorporating stacked capacitors and combined stack-trench capacitors to form column and rows of memory cells. The stacked capacitors and the stack-trench capacitors are alternated to allow improved density, while preventing leakage current and soft errors. Again the stack capacitor and the stack-trench capacitor have a common plate that would be connected to the substrate biasing voltage source V
ss
of
FIGS. 1
a
and
1
c.
U.S. Pat. No. 5,234,854 (An et al.) describes a method for manufacturing a stack-trench capacitor.
U.S. Pat. No. 5,410,509 (Morita) discloses a DRAM array employing a combination of stacked capacitor memory cells and trench capacitor memory cells to form the array. The stacked capacitor memory cells will occupy on column of the array while the trench capacitor memory cells will occupy alternate columns of the memory array. The memory array will also have the stacked capacitor cells and the trench capacitor memory cells used as dummy memory cells within the array. The structure of the memory array is such that when the stacked capacitor memory cells are selected, the dummy stacked memory cells are selected and like wises for the trench capacitor memory cells and the dummy trench capacitor memory cells.
U.S. Pat. No. 5,455,192 (Jeon) describes a method of fabricating a DRAM cell incorporating stacked capacitors and trench capacitors. The structure of the stacked capacitors and the trench capacitors is such that the stacked capacitors and the trench capacitors are connected in parallel to increase the capacitance of the DRAM cell.
SUMMARY OF THE INVENTION
An object of this invention is to provide a DRAM cell capable of storing two bits of digital data as discrete levels of stored charge within the DRAM cell.
Another object of this invention is to provide a DRAM cell incorporating a stacked capacitor and a trench capacitor to retain the discrete levels of charge representing the two bits of digital data.
Further another object of this invention is to provide an array of DRAM cells, each DRAM cell capable of storing two bits of digital data.
Still further another object of this invention is to provide a method of fabrication of a DRAM cell capable of storing two bits of digital data.
To accomplish these and other objects, a twin bit DRAM cell has two pass transistors, a trench capacitor, and a stack capacitor. The first pass transistor has a source connected to a first bit line voltage generator, a gate connected to a word line voltage generator, and a drain. The trench capacitor is placed in close proximity of the first pass transistor and is formed within the semiconductor substrate. The trench capacitor includes a top plate connected to the drain of the first pass transistor, a bottom plate connected to a first biasing voltage source, and a first capacitor dielectric separating the top and bottom plates.
The second pass transistor has a source connected to a second bit line voltage generator, a gate connected to a word line voltage generator, and a drain. The stack capacitor is formed above the trench capacitor on the semiconductor substrate. The stack capacitor has a first plate connected to the dr
Cherng George Meng-Jaw
Chi Min-hwa
Ackerman Stephen B.
Chaudhuri Olik
Coleman William David
Knowles Billy J.
Saile George O.
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