Dram cell and array

Details Dram cell and array Dram cell and array

1984-08-31

1987-03-17

James, Andrew J.

357 234, 357 41, 357 54, 357 59, H01L 2978, H01L 2702, H01L 2934, H01L 2904

Patent

active

046511849

ABSTRACT:
A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one capacitor with both the transistor and the capacitor formed in a trench in a substrate. One capacitor plate and the transistor source are common and are formed in the lower portion of the trench sidewall. The transistor drain is formed in the upper portion of the trench sidewall to connect to a bit line on the substrate surface, and the channel is the vertical portion of the trench sidewall between the source and drain. A ground line runs past the transistor gate in the upper portion of the trench down into the lower portion of the trench to form the other capacitor plate.

REFERENCES:
patent: 4199772 (1980-04-01), Natori et al.
patent: 4353086 (1982-10-01), Jaccodine et al.
patent: 4462040 (1984-07-01), Ho et al.
Chang, T. S. and D. L. Critchlow, "Vertical FET Random-Access Memories with Deep Trench Isolation" IBM Technical Disclosure Bulletin, vol. 22, No. 8B Jan. 1980.

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