Dram CAM cell with hidden refresh

Details Dram CAM cell with hidden refresh Dram CAM cell with hidden refresh

2000-12-06

2002-08-06

Elms, Richard (Department: 2824)

Static information storage and retrieval

Associative memories

Ferroelectric cell

C365S149000

Reexamination Certificate

active

06430073

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
The invention relates generally to semiconductor memory devices, and more specifically to a Dynamic Content Addressable Memory (DCAM) Cell.
2. Related Art
Modern telecommunication networks comprise digital data networks that transmit data in packets or blocks containing address fields for dynamically routing the data packets or blocks through the network (e.g., to the destination address) at high speeds. The fastest searching of stored data may be accomplished using a Content Addressable Memory (CAM).
As the size of networks (e.g., intranets and the Internet) increase the need for larger CAM arrays increases, and accordingly, the need to attach more CAM cells to a common bit line increases. Content Addressable Memory (CAM) arrays of the related art are generally implemented with either conventional Static RAM (SRAM) or conventional destructive-read Dynamic RAM (DRAM) hardware designs, and therefore have all the disadvantages and limitations of one such hardware design or the other.
A typical ternary Static CAM (SCAM) of the relate art contains two six-transistor SRAM storage cells plus an XNOR functional group containing four additional transistors, thus a total of 16 transistors per SCAM cell. An SCAM is generally more vulnerable than a DCAM to corruption of stored data by Soft-Errors (e.g., stored data errors due to exposure of circuits to ambient radiation).
A typical ternary Dynamic CAM (DCAM) cell of the related art may contain fewer transistors than an SCAM, but may have disadvantages including destructive-reads and slower performance. A typical ternary DCAM of the related art includes two data storage capacitors that must be periodically read and refreshed by charge-transfer via pass-transistors that are also used for reading and writing data by charge-transfer, in addition to an XNOR comparison circuit containing four transistors. The charge stored in the data storage capacitors of a DCAM cell is gradually dissipated by leakages within the cell. For this reason, the information stored in the leaking capacitors must be periodically “refreshed,” i.e., the charge is read and then re-written back into the storage cell. The related art provides various DCAM cell structures that are limited in that refresh-reads proceed by charge-transfer thus destroying the data stored in the data-storage capacitors, making the DCAM cell temporarily unavailable for CAM searches until the data is written back into the DCAM cell by a refresh-write. The entire refresh read-write period thereof generally occupies time during which CAM searches can not be performed. Also, limitations of the ability to sense the relatively small charge-transfer from the storage capacitor to a capacitive bit-line coupled thereto limits the maximum array population on such bit-lines, and/or requires larger storage capacitors.
An example of such a destructive-read DCAM is disclosed in U.S. Pat. No. 5,949,696 issued to Threewitt. A variation on the ternary CAM cell disclosed by Threewitt that provides a separate search-line and a separate bit-line for each data storage capacitor of the CAM entry, is depicted in
FIG. 1
, and is similarly limited by an inherently-destructive read. A read operation for a refresh of the DCAM circuit of the related art depicted in
FIG. 1
is performed by charge transfer of the charge stored in a data storage capacitor (e.g. SB
0
or SB
1
) through a pass-Docket transistor (e.g., T
0
R or T
1
R, respectively) and through a bit line (e.g. NBIT or BIT, respectively).
In implementing CAMS, it is desirable to minimize the transistor count and/or CAM cell size, and to increase array utilization. In implementing DCAMs it is desirable to perform the refresh of stored data with minimal delay of or interference with CAM search operation.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides, among other things, an improved Dynamic Content Addressable Memory (DCAM) cell topology that contains fewer than the 16 transistors of the typical Static Content Addressable Memory (SCAM) of the related art, but that can perform a “hidden” refresh of stored data that does not delay nor interrupt the CAM search cycle, thereby providing SCAM-like performance. The inventive DCAM achieves its search performance by simultaneously comparing all entries stored in the memory with an externally applied “comparand.” Words stored in entries in the CAM, which “match” the comparand result in maintaining the non-conductive barrier preventing charge transfer between their respective Match Lines and ground. Conversely, all words stored in entries that contain even a single bit that mismatches (i.e., does not match) the corresponding comparand bit results in a conducting path between each of their Match Lines and ground. Embodiments of the invention provide a non-destructive read operation, such that the stored-data does not have to be written back because of a refresh-read operation; and a reliable CAM search can be performed after a read operation and before or even while the refresh-data is being written back. Soft-error detection processes well known to persons skilled in the art may be performed on each CAM entry during the a pendency of the refresh cycle (or independent of the refresh cycle) without delaying or interrupting CAM search operations. Embodiments of the invention provide CAM cell circuit topologies that can allow more CAM cells to be tied to a read-bit-line of a CAM array than may be tied to a read-bit-line of a DCAM array the related art, thus resulting in greater array utilization.
A first aspect of the invention provides a digital system that performs the function of a network router, and a CAM array having a CAM cell including: a data storage device; a pass-gate including a stack of first and a second pass-switches, the First Pass-Switch being coupled to in series with the Second Pass-Switch at a Node; a Data Storage Device operatively controlling the Second Pass-Switch; and a Third Pass-Switch connected to the Node for detecting the logic state of the Data Storage Device.
A second aspect of the invention provides a method for performing a plurality of CAM searches in a CAM array having a CAM entry that has a word of searchable data stored in a plurality of storage capacitors, comprising the steps of performing a non-destructive determination of the word and subsequently performing a CAM search.
The foregoing and other features of the invention will be apparent from the following more particular description of embodiments of the invention, as illustrated in the accompanying drawings.


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IBM Technical Disclosure Bulletin 31, Mar. 1989, Content Addressable Memory Structures, pp. 1-4.
IBM Technical Disclosure Bulletin, Feb. 1989, DRAM Current Gain Cell With Local Refresh, pp. 1-2.
Mosaid Technologies Incorporated, The Next Generation of Content Addressable Memories, Sep. 1999, 7 pages.

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