DRAM cache

Details DRAM cache DRAM cache

1996-08-09

2000-03-28

Chan, Eddie P.

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

711118, G06F 1208

Patent

active

060444339

ABSTRACT:
A dynamic memory is described which uses a multiplexed latch architecture and global bit lines. The multiplexed architecture allows the memory to operate as a synchronous pipelined cache memory in a computer processing system. The global bit lines are fabricated parallel to memory array bit lines and input/output connections are distributed around the memory to increase speed. Page access operations are controlled to allow either single or burst writes.

REFERENCES:
patent: 4870622 (1989-09-01), Aria et al.
patent: 5159676 (1992-10-01), Wicklund et al.
patent: 5276843 (1994-01-01), Tillinghast et al.
patent: 5577223 (1996-11-01), Tanoi et al.
patent: 5586078 (1996-12-01), Takase et al.
patent: 5596521 (1997-01-01), Tanaka et al.
patent: 5699317 (1997-12-01), Sartore et al.
patent: 5712827 (1998-01-01), Ogihara et al.
patent: 5721862 (1998-02-01), Sartore et al.
patent: 5734614 (1998-03-01), Tsuruda et al.
patent: 5787457 (1998-07-01), Miller et al.
patent: 5802002 (1998-09-01), Ienaga

Affiliated with

Also associated with

Rating

DRAM cache does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DRAM cache, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DRAM cache will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-1335412