DRAM auto-swapping device

Details DRAM auto-swapping device DRAM auto-swapping device

1999-12-10

2003-03-18

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C713S001000

Reexamination Certificate

active

06535992

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an auto-swapping device. More specifically, it relates to a DRAM auto-swapping device. When the first 64K memory segment of a DRAM module in a computer fails to pass the BIOS testing, the auto-swapping device will access the other available memory segments of the DRAM module automatically such that the computer system can be activated.
2. Description of the Related Art
When a computer system is turned on, the BIOS of the computer system first performs a power on self-test (hereinafter referred as POST). The computer system is then activated after the POST process is completed normally. During the POST process, if the first memory segment (for example, the first 64K memory segment) of a DRAM module equipped in the computer system fails to pass the POST, the computer system is suspended or halted and not able to be activated. Thus, the computer system can not be activated due to the failure of a small memory space (only 64K memory) in the DRAM module. Even though the DRAM module has other available memory segments, they can not be used for activating the computer system.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a DRAM auto-swapping device to access the other available memory segments of a DRAM module automatically such that the computer system equipped with the DRAM module can be activated, even when the first memory segment (the first 64K memory segment) of the DRAM fails in the POST process.
The present invention achieves the above-indicated objects by providing a DRAM auto-swapping device, which comprises: an output-port selecting device for selectively enabling a specific output port to output a specific value; and a swap-selection device receiving a first-address signal set, for outputting the first-address signal set or a second-address signal set to access the DRAM according to the output value of the specific output port, wherein the second-address signal set is obtained by carrying out logic operation on the first-address signal set.
When the BIOS does not detect failure of the first 64K memory segment of the DRAM, the swap-selection device outputs the first-address signal set for accessing the first 64K memory segment of the DRAM and the BIOS keeps performing the testing process to activate the computer system.
When the BIOS detects failure of the first 64K memory segment of the DRAM, the output-port selecting device enables the specific output port to output the specific value such that the swap-selection device outputs the second-address signal set for accessing the available memory segments of the DRAM, and the BIOS keeps performing the testing process to activate the computer system.


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patent: 5708791 (1998-01-01), Davis
patent: 6035420 (2000-03-01), Liu et al.
patent: 6185696 (2001-02-01), Noll

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