DRAM array and electronic system

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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Details

C257SE29345, C438S253000, C438S396000

Reexamination Certificate

active

07573088

ABSTRACT:
The invention includes a semiconductor construction including rows of contact plugs, and rows of parallel bottom plates. The plug pitch is approximately double the plate pitch. The invention includes a method of forming a semiconductor construction. A plurality of conductive layers is formed over the substrate, the plurality of layers being substantially orthogonal relative to first, second and third rows of contact plugs. An opening is etched which passes through each of the conductive layers within the plurality of conductive layers. The opening is disposed laterally between the first and second row of contact plugs. After etching the opening a dielectric material is deposited over the plurality of conductive layers and a second conductive material is deposited over the dielectric material. The invention includes an electronic system including a processor and a memory operably associated with the processor. The memory device has a memory array which includes double-pitched capacitors.

REFERENCES:
patent: 6025624 (2000-02-01), Figura
patent: 6914286 (2005-07-01), Park
patent: 7188038 (2007-03-01), Picollet et al.
patent: 7300841 (2007-11-01), Park
patent: 2001/0000492 (2001-04-01), Figura
patent: 2003/0085420 (2003-05-01), Ito et al.
patent: 2005/0051822 (2005-03-01), Manning
patent: 2005/0082586 (2005-04-01), Tu et al.
patent: 2006/0121672 (2006-06-01), Basceri et al.
patent: 19639899 (1998-04-01), None

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