Electrical computers and digital processing systems: memory – Storage accessing and control – Shared memory area
Patent
1996-02-07
1998-09-15
Swann, Tod R.
Electrical computers and digital processing systems: memory
Storage accessing and control
Shared memory area
711106, 711167, 395293, 395520, 395728, 395729, G06F 1200
Patent
active
058095381
ABSTRACT:
A memory control and management system efficiently multiplexes access to a dynamic random access memory (DRAM) among several client processes in an MPEG or similar digital television delivery system or the like. These processes can include, for example, an on-screen display (OSD) graphics processor, a microprocessor interface, graphics accelerator functions, and audio and data processors. An arbiter receives packetized data from an MPEG transport layer for distribution to an associated DRAM. The arbiter sequentially time-multiplexes access to the DRAM by the client processes according to priority criteria, including the bandwidth requirements of the client processes, and whether a client process is requesting access. Access is granted for a predetermined period as long as the client is requesting access. Access can be terminated early if the client no longer requests access, or if a new row in the DRAM must be addressed, and the re-addressing period will consume the remainder of the available data transfer cycles in the access period. The invention is particularly applicable to a digital video decoder where an on-screen display graphics processor consumes a large portion of the DRAM interface bandwidth.
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Pollmann Stephen C.
Yilmaz Serdar
General Instrument Corporation
Hoppin Ralph F.
Lipsitz Barry R.
Swann Tod R.
Tzeng Fred Fei
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