DRAM and refresh method thereof

Details DRAM and refresh method thereof DRAM and refresh method thereof

2005-12-20

2005-12-20

Yoha, Connie C. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Data refresh

C365S230030, C365S225700, C365S201000

Reexamination Certificate

active

06977857

ABSTRACT:
The present invention relates to a DRAM having a memory array that is divided into a plurality of memory blocks. A memory block having a long data retention time is selected from the plurality of memory blocks and a logical address is allocated to the selected memory block. The selected memory block is refreshed at longer time intervals compared to conventional DRAMs resulting in lower power consumption.

REFERENCES:
patent: 5530674 (1996-06-01), McClure et al.
patent: 5596535 (1997-01-01), Mushya et al.
patent: 6208570 (2001-03-01), Brown et al.
patent: 6577534 (2003-06-01), Tsuruda
patent: 6760806 (2004-07-01), Jeon

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