DRAM and data access method for DRAM

Details DRAM and data access method for DRAM DRAM and data access method for DRAM

1999-12-16

2001-06-26

Nelms, David (Department: 2818)

Static information storage and retrieval

Systems using particular element

Capacitors

C365S233100

Reexamination Certificate

active

06252794

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a DRAM (Dynamic random access memory) and a data access (read/write) method for the DRAM.
BACKGROUND
A dynamic RAM (DRAM) is generally used as a mass storage RAM. In a DRAM, a memory cell is specified by using a row address (corresponding to a word line
82
) and a column address (corresponding to a bit line
84
) as is shown in
FIG. 3
, so that data can be written in or read from the specified memory cell. The outline of timing of data read is illustrated in FIG.
4
(
a
). First, an address signal is input to a row decoder
72
so as to specify a row address. Then, all data on a word line
80
corresponding to the specified row address are read through the bit lines
84
to sense amplifiers
74
. Next, an address signal is input to a column decoder
76
so as to specify a column address. Then, among the data having been read to the sense amplifiers
74
, data on a bit line corresponding to the specified column address is specified to be output. In this manner, data are read or written by specifying a row address and a column address.
However, when data on the same word line (namely, having the same row address) are to be continuously read, the target data are already read to the sense amplifiers, and hence, there is no need to read the data on this word line to the sense amplifiers
74
again. Accordingly, in this case, the outline of timing of data read can be substantially illustrated as in FIG.
4
(
b
). In this manner, when data on the same word line are to be continuously read, merely a column address is specified. Therefore, the data can be more rapidly output than the timing shown in FIG.
4
(
a
).
Moreover, in a synchronous DRAM (SDRAM), an address is automatically generated therein without specifying a column address as shown in FIG.
4
(
b
), so as to output data in synchronization with a clock. The outline of this data read is illustrated in FIG.
5
. In this case, by specifying read start addresses (row and column addresses) and a bank, data with a predetermined burst length are continuously output in synchronization with a clock. In this manner, since the SDRAM outputs data every clock, the data can be further rapidly output than in the timing of the page mode shown in FIG.
4
(
b
).
Recently, generation-to-generation improvement in the operation speed of a DRAM is largely behind that of an MPU, and the improvement in the operation speed of a DRAM has become a significant problem. Accordingly, an SDRAM with a large bandwidth has become a leading memory. The bandwidth of an SDRAM is increased by utilizing the burst mode in which data in continuous addresses having a burst length of 2, 4 or 8 bits are written and read from a sense amplifier for latching data on the same word line (namely, having the same row address) in synchronization with a fast clock. However, an SDRAM is scarcely different from a general DRAM in the basic structure as a memory except for the system of continuously outputting data synchronously with a clock. In other words, data read to the sense amplifiers are dealt with in substantially the same manner as in the page mode shown in FIG.
4
(
b
) except that the data can be continuously accessed by a new method such as pipeline processing.
Accordingly, all disadvantages of a general DRAM except for one that can be overcome by continuously dealing with data synchronously with a clock still remain in an SDRAM as disadvantages. For example, access times from the specification of a row address and a column address of an SDRAM are substantially equal to those of a general DRAM. Also, an SDRAM has no specific means for improving a cycle time. Furthermore, since an initial access time and a cycle time are long, it is needless to say that the latency for these processing is long. In addition, when different row addresses are continuously accessed, a long idle time is unavoidably caused in an interval between data processing in the burst mode. Accordingly, there arises a serious problem that a substantial data transfer rate cannot be improved.
Furthermore, in such a DRAM and SDRAM, fast access is realized by specifying a column address alone of data having been latched by the sense amplifier. Accordingly, in order to utilize data on an activated word line as efficiently as possible, a very large page length is generally adopted. For example, a 64-Mbit DRAM has a page length of 512 through 1024 bits, and in the entire chip, 8 k through 16 k (1 k=1024) sense amplifiers are simultaneously activated. However, even when the burst mode is repeated, 256 bits at most are used in an SDRAM, and further fewer bits are used in a DRAM. Thus, an unnecessarily large number of sense amplifiers are activated, and the utilization ratio of the sense amplifiers is very low.
The number of sense amplifiers simultaneously activated tends to be increasing in accordance with the development of generations of DRAMs. The activation of such a large number of sense amplifiers is one of the causes for obstructing a decrease of restore and precharge times and an improvement of the access time and the cycle time. The same is true for an SDRAM, and in such a device in the 64-Mbit class, an RAS (Row address strobe) access time (RAS latency) of 50 through 60 ns, an address access time (CAS (Column address strobe) latency) of 25 through 30 ns and a cycle time of 80 through 90 ns are available at most at present. When these times are long, there arises a long latency time between bursts in making continuous accesses to different row addresses, which makes it difficult to improve the substantial data transfer rate. This leads to a serious problem because a memory will be used with randomly changing row addresses in the multi-task environment further developing.
SUMMARY OF THE INVENTION
An object of the invention is, even in making continuous random row accesses with row addresses changing in every access to a DRAM, minimizing or eliminating a latency time between bursts, so as to attain a substantial data transfer rate approximate to or according with a maximum value obtained based on a clock frequency.
The DRAM of this invention comprises plural DRAM cells; sense amplifiers respectively corresponding to the plural DRAM cells; and means for activating merely a sense amplifier corresponding to a cell to be accessed among the plural DRAM cells.
The data access (read/write) method for a DRAM of this invention comprises the steps of selecting a cell to be accessed among plural DRAM cells; and activating merely a sense amplifier corresponding to the selected cell.


REFERENCES:
patent: 5581512 (1996-12-01), Kitamura
patent: 5600605 (1997-02-01), Schaefer
patent: 5867447 (1999-02-01), Koshikawa
patent: 5923595 (1999-07-01), Kim
patent: 5991223 (1999-11-01), Kozaru et al.
patent: 6088291 (2000-07-01), Fujioka et al.

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