DQS postamble filtering

Details DQS postamble filtering DQS postamble filtering

2006-04-18

2006-04-18

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Addressing

Sync/clocking

C365S189080, C326S038000

Reexamination Certificate

active

07031222

ABSTRACT:
Circuits, methods, and apparatus for filtering signals at a high-speed data interface. One exemplary embodiment is particularly configured to filter a clock signal at the end of a data burst received by a double-data rate memory interface. A clock input port is either connected or disconnected to an input cell. When a data burst is to be received, the clock input port is connected to the input cell. When the data burst concludes, the clock input port is disconnected from the input cell. In a specific embodiment, a signal is received indicating that a data burst is about to begin and the clock input port is connected to the input cell. The signal later changes state indicating that the last data bit is being received. When the last clock edge corresponding to the last data bit is received, the clock input port is disconnected from the input cell.

REFERENCES:
patent: 5898702 (1999-04-01), Narayanan et al.
patent: 6472904 (2002-10-01), Andrews et al.
patent: 6525565 (2003-02-01), Young et al.

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