DQS for data from a memory array

Details DQS for data from a memory array DQS for data from a memory array

2007-02-27

2007-02-27

Auduong, Gene N. (Department: 2827)

Static information storage and retrieval

Read/write circuit

Signals

C365S194000, C365S189050

Reexamination Certificate

active

10967768

ABSTRACT:
A memory comprises a first circuit, a second circuit, and a latch. The first circuit is configured to provide a first signal indicating an earliest time valid data is available from a memory array in response to a read command. The second circuit is configured to provide a second signal indicating a latest time valid data is available from the memory array in response to the read command. The latch is configured to be connected to a data line coupled to the memory array in response to the first signal and disconnected from the data line in response to the second signal to latch data read from the memory array.

REFERENCES:
patent: 5383155 (1995-01-01), Ta
patent: 5436865 (1995-07-01), Kitazawa
patent: 5502681 (1996-03-01), Park
patent: 5550784 (1996-08-01), Takai
patent: 5802002 (1998-09-01), Ienaga
patent: 5948083 (1999-09-01), Gervasi
patent: 6664838 (2003-12-01), Talledo
patent: 6760263 (2004-07-01), Liou
patent: 6856558 (2005-02-01), Proebsting et al.
patent: 0 624 878 (1994-11-01), None
patent: 0 526 433 (1996-02-01), None
PCT Internation Search Report for International Application No. PCT/ep2005/010787 mailed on Feb. 24, 2006 (6 pgs.).

Affiliated with

Also associated with

Rating

DQS for data from a memory array does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with DQS for data from a memory array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and DQS for data from a memory array will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3889490