Double-spacer technique for forming a bipolar transistor with a

Details Double-spacer technique for forming a bipolar transistor with a Double-spacer technique for forming a bipolar transistor with a

1995-09-29

1999-02-02

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Forming bipolar transistor by formation or alteration of...

Self-aligned

438368, 438309, H01L 21331

Patent

active

058664629

ABSTRACT:
Emitter widths of 0.3 .mu.m on double polysilicon bipolar transistors are achieved using O.8 .mu.m photolithography and a double spacer process. The emitter width reduction is confirmed with structural and electrical measurements. The double-spacer device exhibits superior low current f.sub.T and f.sub.max.

REFERENCES:
patent: 4581319 (1986-04-01), Wieder et al.
patent: 5023192 (1991-06-01), Josquin et al.
patent: 5424228 (1995-06-01), Imai
patent: 5512785 (1996-04-01), Haver et al.

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