Double silicide formation in polysicon gate without silicide...

Details Double silicide formation in polysicon gate without silicide... Double silicide formation in polysicon gate without silicide...

2000-10-05

2002-09-17

Thomas, Tom (Department: 2825)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S652000, C438S655000, C438S664000, C438S683000

Reexamination Certificate

active

06451693

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to semiconductor fabrication, and in particular to forming silicide contacts on a semiconductor device.
BACKGROUND OF THE INVENTION
The semiconductor industry is continually striving to improve the performance of metal-oxide-semiconductor (MOS) devices. The ability to create devices with sub-micron features has allowed significant performance increases, due to a resulting decrease in the resistances and parasitic capacitances that adversely affect performance. The attainment of sub-micron features has been accomplished via advances in several semiconductor fabrication disciplines. For example, the development of more sophisticated exposure cameras in photolithography, as well as the use of more sensitive photoresist materials, have allowed sub-micron features, in photoresist layers, to be routinely achieved. Additionally, the development of more advanced dry etching tools and processes have allowed the sub-micron images in photoresist layers to be successfully transferred to underlying materials used in MOS structures.
In addition to the contributions supplied by these advances in MOS processing disciplines, performance improvements have also been obtained through use of a salicide process (Self-ALIgned-siliCIDE). Salicide technology comprises forming silicide layers on the source/drain regions and/or on the gate electrode in a self-aligned manner. Salicide technology is improving the performance characteristics of semiconductor devices, and is becoming an essential component of semiconductor device fabrication. As gate electrode lengths are scaled down, the source/drain junctions and polycrystalline line width must also be scaled down. However, scaling down the source/drain junctions and polycrystalline line width increases parasitic resistance in the source/drain diffusion layers and gate electrode diffusion layer, and also increases the sheet and contact resistance of the gate electrode and source/drain regions. Salicide technology reduces parasitic, sheet, and contact resistance in the source/drain diffusion layers and the gate electrode diffusion layer that results from this scaling down of the source/drain junctions and polycrystalline line width.
Silicides are typically formed by reacting a metal with crystallized silicon (Si) within a specified temperature range for a specific period of time. Silicide layers may be self-aligned by different techniques. For example, selectively depositing the metal on the top of the gate electrode and on the source/drain regions of a semiconductor device prior to an annealing process causes only the Si of the source/drain regions and the top of the gate electrode to form silicide upon annealing. Alternatively, sidewall spacers, on the sides of the gate electrode, constructed of a material that does not react with the metal layer, allow a blanket layer of metal to be deposited over a semiconductor device while restricting silicide formation to the exposed source/drain regions and the top of the gate electrode during an annealing process. During the annealing process, the semiconductor device is heated to a reaction temperature, and held at the reaction temperature for a period of time, causing the metal layer to react with the crystallized Si that the metal contacts, thus forming a silicide layer interfacing with the remaining crystallized Si substrate of the source/drain regions and/or the gate electrode. Multiple annealing steps may be employed. Various metals react with Si to form a silicide, however, titaniumn (Ti) and cobalt (Co) are currently the most common metals used to create silicides when manufacturing semiconductor devices utilizing salicide technology. Recently, attention has turned towards using nickel to form NiSi utilizing salicide technology. Using NiSi is advantageous over using TiSi
2
and CoSi
2
because many limitations associated with TiSi
2
and CoSi
2
are avoided. When forming NiSi, a low resistivity phase is the first phase to form, and does so at a relatively low temperature. Additionally, nickel (Ni), like Co, diffuses through the film into Si, unlike Ti where the Si diffuses into the metal layer. Diffusion of Ni, and Co, through the film into Si prevents bridging between the silicide layer on the gate electrode and the silicide layer over the source/drain regions. The reaction that forms NiSi requires less Si than when TiSi
2
and CoSi
2
are formed. Nickel silicide exhibits almost no linewidth dependence of sheet resistance. Nickel silicide is normally annealed in a one step process, versus a process requiring an anneal, an etch, and a second anneal, as is normal for TiSi
2
and CoSi
2
. Nickel silicide also exhibits low film stress, i.e., causes less wafer distortion.
As shown in
FIG. 1
, a typical semiconductor device, a metal oxide semiconductor field effect transistor (MOSFET), includes a polysilicon gate
100
and an insulating gate oxide layer
110
formed over silicon substrate
120
. Deep source/drain regions
140
(sometimes referred to as heavily doped source and drain regions) and source/drain extension regions
150
(sometimes referred to as lightly doped source and drain regions or LDDs) are formed in substrate
120
, such as by ion implantation. Typically, once the source/drain extension regions
150
are formed, oxide spacers are formed abutting the gate
100
to protect the source/drain extension regions from further doping while additional ion implantation is performed to form the deep source/drain regions
140
. The source/drain extension
150
and deep source/drain
140
are annealed (heated) following ion implantation to obtain the desired material characteristics and to activate the dopants. Generally, doped regions are regions containing a higher concentration of p-type or n-type dopants than the substrate. Also, silicide regions
170
and
160
are typically formed on, over, or within the polysilicon gate
100
and the source/drain regions
140
, respectively.
Source/drain extension regions
150
generally have a lower concentration of dopants compared to deep source/drain regions
140
, although extension regions
150
are increasingly being endowed with dopant concentrations approaching that of the deep source/drain regions
140
. Source/drain extension regions
150
possess a thickness T
1
smaller than a corresponding thickness T
2
of deep source/drain regions
140
. The shallow source/drain extension regions
150
are important, for example, in reducing hot carrier injection (HCI) which often occurs in scaled down (e.g., sub-micron) devices and in reducing short channel effects. For adequate suppression of short channel effects (SCE), the depth of the source drain extension regions should be less than about 700 Å and preferably less than about 500 Å and still more preferably less than 300 Å.
A conventional process for forming the MOSFET shown in
FIG. 1
is illustrated in
FIGS. 2A-2G
. Such a process begins with a substrate
200
upon which is deposited or grown an oxide or other insulating layer. A polysilicon layer or layer of other conducting material is formed over the oxide layer followed by patterning and etching to form gate oxide
205
and polysilicon gate
210
, as shown in FIG.
2
A. Source/drain extension regions
220
are then formed as shown in
FIG. 2B
, generally by ion implantation with boron, arsenic, or phosphorous ions at energy levels in the range of 1-100 keV. Some processes perform an anneal step following this step to activate doped extension regions
220
. Following formation of source/drain extension regions
220
, spacers
230
are formed abutting the gate
210
to protect the underlying source/drain extension regions from subsequent implantation used to form the deep source/drain regions
240
. The spacers are typically formed by depositing an oxide layer over the entire wafer, including the substrate and gate, by chemical vapor deposition (CVD) or other well-known method followed by anisotropic etching of the oxide to form the spacers
230
, as shown in FIG.
2
C.
Once spacers

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