Double sidewall raised silicided source/drain CMOS transistor

Details Double sidewall raised silicided source/drain CMOS transistor Double sidewall raised silicided source/drain CMOS transistor

1998-07-10

2002-04-09

Wilczewski, Mary (Department: 2822)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S655000, C438S664000, C438S682000, C438S154000, C438S230000, C438S233000, C438S303000, C438S586000

Reexamination Certificate

active

06368960

ABSTRACT:

FIELD OF THE INVENTION
This invention relates to high performance CMOS formed on SIMOX and MOS transistors having very short channel length with shallow source and drain regions.
BACKGROUND OF THE INVENTION
MOS circuits generally use a refractory metal, or silicide of a refractory metal, as a barrier, a conducting media, or an intermediate layer. Refractory metals and their silicides have relative low resistivities and low contact resistances and are desirable as conducting films and layers. Known salicide processes, however, fail to work on deep sub-micron MOS transistors because such processes generally consumes too much silicon. Additionally, impurities and problems achieving uniform deposition of silicide layers create manufacturing problems. Selective epitaxial deposition of silicon or selective deposition of polysilicon requires specialized manufacturing equipment. In addition, the selectivity of the salicide process is strongly dependant on the surface condition of the annealed film.
SUMMARY OF THE INVENTION
The method of the invention for forming a silicided device includes preparing a substrate by forming device areas thereon; providing structures that are located between the substrate and any silicide layers; forming a first layer of a first reactive material over the formed structures; providing insulating regions in selected portions of the structure; forming a second layer of a second reactive material over the insulating regions and the first layer of first reactive material; reacting the first and second reactive materials to form silicide layers; removing any un-reacted reactive material; forming structures that are located on the silicide layers; and metallizing the device.
It is an object of this invention to develop a simple, reliable, and cost effective salicide CMOS process/structure for very high density very small geometry circuit fabrication.


REFERENCES:
patent: 5365111 (1994-11-01), Ramaswami et al.
patent: 5464782 (1995-11-01), Koh
patent: 5648287 (1997-07-01), Tsai
patent: 5691212 (1997-11-01), Tsai
patent: 5733803 (1998-03-01), Mueller
patent: 0 480 446 (1992-04-01), None
patent: 0 766 305 (1992-04-01), None
patent: 07030104 (1995-01-01), None
patent: WO 98/35380 (1998-08-01), None

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