Semiconductor device manufacturing: process – Chemical etching – Combined with coating step
Reexamination Certificate
2006-07-25
2006-07-25
Le, Dung A. (Department: 2818)
Semiconductor device manufacturing: process
Chemical etching
Combined with coating step
C438S106000, C438S107000, C438S022000, C029S830000
Reexamination Certificate
active
07081412
ABSTRACT:
Double-sided etching techniques are disclosed for providing a semiconductor structure with one or more through-holes. The through-holes may be sealed hermetically such as by a feed-through metallization process. The feed-through metallization process may provide electrical contact to an opto-electronic or integrated circuit encapsulated in a package with the semiconductor structure used as a lid.
REFERENCES:
patent: 4897711 (1990-01-01), Blonder et al.
patent: 4903120 (1990-02-01), Beene et al.
patent: 4904036 (1990-02-01), Blonder
patent: 5023881 (1991-06-01), Ackerman et al.
patent: 5068203 (1991-11-01), Logsdon et al.
patent: 5308442 (1994-05-01), Taub et al.
patent: 5454161 (1995-10-01), Beilin et al.
patent: 5656507 (1997-08-01), Welbourn et al.
patent: 5703394 (1997-12-01), Wei et al.
patent: 5891354 (1999-04-01), Lee et al.
patent: 5898806 (1999-04-01), Nishimoto
patent: 6028001 (2000-02-01), Shin
patent: 6036872 (2000-03-01), Wood et al.
patent: 6072815 (2000-06-01), Peterson
patent: 6117794 (2000-09-01), Dormer et al.
patent: 6139761 (2000-10-01), Ohkuma
patent: 6221769 (2001-04-01), Dhong et al.
patent: 6291779 (2001-09-01), Lubert et al.
patent: 6577427 (2003-06-01), Gee et al.
patent: 6660564 (2003-12-01), Brady
patent: 2002/0104681 (2002-08-01), Ishiwa et al.
patent: 2004/0025333 (2004-02-01), Hirose et al.
patent: 0 430 593 (1991-06-01), None
patent: 0 795 766 (1997-09-01), None
patent: 0 884 782 (1998-12-01), None
patent: 1 061 578 (2000-12-01), None
patent: 2001-091794 (2001-04-01), None
patent: WO 00/07225 (2000-02-01), None
patent: WO 00/41281 (2000-07-01), None
patent: WO 01/24228 (2001-04-01), None
Linder et al., “Fabrication Technology for Wafer Through-Hole interconnections and three-Dimensional Stacks of Chips and Wafers,” Micro Electro Mechanical Systems, 1994, MEMS '94, Proceedings, IEEE Workshop on Oiso, Japan Jan. 25-28, 1994, New York, NY, USA, IEEE, pp. 349-351.
Mita Y. et al., “Embedded-Mask-Methods for mm-scale multi-layer vertical/slanted Si structures,” Proceedings IEEE thirteenth Annual International Conference on Micro electro Mechanical Systems, Jan. 23-27, 2000, pp. 300-305.
Hymite A/S
Le Dung A.
LandOfFree
Double-sided etching technique for semiconductor structure... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Double-sided etching technique for semiconductor structure..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Double-sided etching technique for semiconductor structure... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3561466