Double scan circuit for inserting a new scan line between adjace

Details Double scan circuit for inserting a new scan line between adjace Double scan circuit for inserting a new scan line between adjace

1994-10-21

1995-12-12

Metjahic, Safet

Television

Format conversion

Line doublers type

348441, 348561, 345130, 345200, H04N 701, H04N 5262

Patent

active

054754372

ABSTRACT:
A double scan circuit has first and second data converters for converting n-bit real line data and n-bit interpolated line data into 2n-bit data; first and second RAMs in which the real line data and the interpolated line data are stored, respectively; a memory controller for generating a write/read control signal for the first and the second RAMs, a write address and a read address whose speed is double that for the write address, for outputting them to the first and second RAMs, and for generating a mixing control signal for mixing the original line data and the interpolated line data stored in the first and second RAMs for double scanning; and a multiplexer for selecting one between the 2n-bit real line data and the 2n-bit interpolated line data generated from the first and second RAMs in accordance with the mixing control signal and the real/interpolated line control signal and for producing the selected one as n-bit double scan data. This circuit facilitates VLSI implementation compared with a conventional double scan circuit using FIFO-type memories.

REFERENCES:
patent: 4573080 (1986-02-01), Maze
patent: 4605962 (1986-08-01), Christopher et al.
patent: 4825288 (1989-04-01), Chantelou
patent: 4868656 (1989-09-01), Geiger et al.
patent: 4959715 (1990-09-01), Prodan
patent: 5115312 (1992-05-01), Shim
patent: 5177609 (1993-01-01), Kawakami et al.

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