Double precision multiplier

Details Double precision multiplier Double precision multiplier

1985-04-25

1988-01-26

Malzahn, David H.

Boots, shoes, and leggings

364745, G06F 752

Patent

active

047220686

ABSTRACT:
A double precision multiplyer for performing the multiplication of two double precision data using a 2's complement single precision multiplier. The 2n-1 bit double precision data is divided into one single precision data formed by taking the upper n bits of the double precision data and another single precision data formed by adding a "0" bit before the most significant bit of the remaining n-1 bits of the double precision data. Apparatus for performing the double precision multiplication thereby eliminates the necessity of discriminating the sign bit and enhances the speed of the double precision multiplication.

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patent: 4507749 (1985-03-01), Ohhashi
Senzig, "Multiple Precision Pipelined Multiplier" IBM Tech. Disclosure Bulletin, vol. 10 No. 4, Sep. 1967, pp. 403-405.
Dauby et al., "Two's Complement Multiplier" IBM Tech. Disclosure Bulletin, vol. 18, No. 5, Oct. 1975, pp. 1482-1483.
Nishitani, et al., "A Single-Chip Digital Signal Processor for Telecommunication" Applications, IEEE Journal of Solid-State Circuits, vol. SC-16, No. 4, pp. 372-376.
McDonough, et al., "Microcomputer with 32-Bit Arithmetic does High-Precision Number Crunching", Electronics, Feb. 24, 1982, pp. 105-110.

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