Double polysilicon electrostatic discharge protection device for

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

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Details

257336, 257337, 257408, 437 49, 437 56, 437233, H01L 2904, H01L 21265

Patent

active

054554446

ABSTRACT:
A semiconductor ESD device on a substrate is covered with SiO.sub.2 and FOX regions, made by forming a blanket first gate layer on the device including the SiO.sub.2 and FOX regions, patterning the first gate layer into an ESD device and a gate in a standard device area separated by a FOX region, forming LDD implantation in the substrate adjacent to the gate in the standard device area, forming spacers adjacent to the periphery of the first gate layer and the gate, ion implanting dopant near the spacers to form source/drain regions adjacent to the standard device, forming an interpolysilicon dielectric layer over the device, forming a polysilicon via mask for the ESD device and etching the interpolysilicon dielectric layer to form a via opening through the mask, deposition of a second gate layer shorted to the first gate layer in the ESD device area and forming a masking layer and etching away exposed areas of the second gate layer and the first gate layer leaving a stacked structure from portions of the first gate and the second gate upon the ESD device, removal of the masking layer, and forming a mask and performing a doping process doping the second gate structure and second source/drain regions in the substrate in the ESD area.

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patent: 5225702 (1993-07-01), Chatterjee
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patent: 5256892 (1993-10-01), Yoshida

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