Double poly-gate high density multi-state flat mask ROM cells

Details Double poly-gate high density multi-state flat mask ROM cells Double poly-gate high density multi-state flat mask ROM cells

1998-07-10

2000-07-18

Tsai, Jey

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

257391, H01L 218246

Patent

active

060911190

ABSTRACT:
The mask ROM cell structure is described as follows: a plurality of first polysilicon gates is formed on the semiconductor substrate, being separated to keep a space. Each of first polysilicon gates comprises first nitride layer/ a n+ polysilicon layer/a first pad oxide layer, and two spacers that formed over the remnant portion of the pad oxide layer, and formed, respectively, on two sidewalls of the first nitride layer 130, and the first n+ polysilicon layer. A plurality of second polysilicon gates is formed on the semiconductor substrate 105. Each of the second polysilicon gates comprises second n+doped polysilicon gate/second pad oxide layer, wherein the pad oxide layer is formed on the semiconductor substrate, and the n+doped polysilicon gate is formed on the second pad oxide layer. The first polysilicon gates separate the second polysilicon gates each.

REFERENCES:
patent: 5556800 (1996-09-01), Takizawa et al.
patent: 5576573 (1996-11-01), Su et al.
patent: 5585297 (1996-12-01), Sheng et al.
patent: 5683925 (1997-11-01), Irani et al.
T.P. Ong, CVD SiN.sub.x Anti-reflective Coating for Sub-0.5.mu.m Lithography, 1995 Symposium on VLSI Technology Digest of Technical Papers, Apr. 1995, pp. 73-74.
Bertagnolli et al., RCS: An Extremely High Density Mask ROM Technology Based On Vertical Transistor Cells, 1996 Symposium on VLSI Technology Digest of Technical Papers, pp. 58-59.

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