Double planarization process for multilayer metallization of int

Details Double planarization process for multilayer metallization of int Double planarization process for multilayer metallization of int

1984-04-04

1984-11-06

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156651, 156657, 204192E, B44C 122, C03C 1500, C03C 2506

Patent

active

044810709

ABSTRACT:
A process is disclosed for the planarization of an integrated circuit structure by a two stage planarization process which comprises: applying over a metallization layer, having one or more openings therein, a layer of insulation sufficiently thin to avoid formation of voids in the portion of the insulation applied in the openings in the metallization layer; smoothing the insulation layer by removing the high portions of the insulation by, for example, dry etching the insulation; applying a further layer of insulation over the first insulation layer; and smoothing the further layer of insulation by removing the high portions by, for example, dry etching; whereby the resultant smoothed insulation surface will be substantially planar and substantially void-free. In a preferred embodiment, a second material, such as a photoresist material, is coated over the insulation layer prior to the smoothing step, particularly when an anisotropic dry etching process is used, to insure that only the high portions of the insulation layer are removed in the etching step.

REFERENCES:
patent: 4089766 (1978-05-01), Paal et al.
patent: 4377438 (1983-03-01), Moriya et al.
patent: 4451326 (1984-05-01), Gwozdz

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