1988-02-12
1989-11-28
James, Andrew J.
357 42, 357 71, H01L 2952, H01L 2978, H01L 2710
Patent
active
048841188
ABSTRACT:
A gate array is provided in which active areas within the substrate are arranged in alternating columns of opposite conductivity type and symmetrical about the center lines through each column so that CMOS devices can be advantageously formed by allocating only small increments of active area to metal routing. The substrate and well taps are also symmetrical about the column center line. The active area symmetry allows p-channel and n-channel transistors to be combined where the p-channel transistor is on either the right or left, thus increasing the flexibility in placing the elements within the integrated circuit chip.
REFERENCES:
patent: 4280272 (1981-07-01), Egawa et al.
patent: 4412237 (1983-10-01), Matsumura et al.
patent: 4701777 (1987-10-01), Takayama et al.
Dell'Oca Conrad J.
Hui Alex C.
Szeto Roger
Wong Anthony Y.
Wong Daniel
Jackson, Jr. Jerome
James Andrew J.
LSI Logic Corporation
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