Double layer photoresist technique for side-wall profile control

Details Double layer photoresist technique for side-wall profile control Double layer photoresist technique for side-wall profile control

1985-04-29

1987-02-24

Powell, William A.

Adhesive bonding and miscellaneous chemical manufacture

Delaminating processes adapted for specified product

Delaminating in preparation for post processing recycling step

156644, 156646, 156652, 156653, 156657, 1566611, 156668, 156904, 20419232, 427 38, 427 88, 357 65, 430312, 430313, 430317, B44C 122, C03C 1500, C03C 2506, B29C 1708

Patent

active

046455620

ABSTRACT:
A photolithographic process useful for VLSI fabrication is disclosed for achieving side-wall profile control of poly lines, metal lines, contact and via openings. Layers of a first and second photoresist materials are formed on the poly, metal or oxide-covered substrate. The top layer is patterned by conventional processes to define the final device geometry. The bottom layer is exposed and over-developed to form an overhang structure about the line pattern or the contact/via opening. During the subsequent anisotropic plasma-assisted etching step, some ions or particles are passed obliquely over the overhang and bombard the opening corner, the side-wall and the under-cut area. The plasma-assisted etching step not only forms the poly or metal lines, or the contact or via opening, but also results in an opening with rounded corners and a smoothly tapered side-wall profile. The subsequent metal film deposition step results in a uniform film thickness around the edges of the opening. The process thus alleviates the problem of high contact resistance previously encountered as a result of dry etching the contact or via openings.

REFERENCES:
patent: 4354897 (1982-10-01), Nakajima
patent: 4461672 (1984-07-01), Musser
patent: 4484978 (1984-11-01), Keyser
patent: 4523976 (1985-06-01), Bukhman
IBM Journal of Research and Development, vol. 26, No. 5, Sep. 1982, A. S. Bergendahl et al, "Optimization of Plasma Processing for Silicon Gate FET Manufacturing Applications", pp. 580-589.
Solid State Technology, vol. 22, No. 4, Apr. 1979, P. D. Parry et al, "Antisotropic Plasma Etching of Semiconductor Materials", pp. 125-132.
IBM Technical Disclosure Bulletin, vol. 22, No. 1, Jun. 1979, J. S. Logan et al, "Process for Forming Tapered Vias in SiO.sub.2 by Reactive Ion Etching", pp. 130-132.
Solid State Technology, vol. 27, No. 4, Apr. 1984, J. S. Chang, "Selective Reactive Ion Etching of Silicon Dioxide", pp. 214-219.
IBM Technical Disclosure Bulletin, vol. 22, No. 11, Apr. 1980, K. Chang et al, "Method for Controlling Via Sidewall Slope", pp. 4883-4885.
Patents Abstracts of Japan, vol. 6, No. 9, Jan. 20, 1982.

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