Double-gated transistor circuit

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Charge transfer device

Reexamination Certificate

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C257S347000

Reexamination Certificate

active

07019342

ABSTRACT:
An OR gate circuit includes double-gated four terminal transistor with independent gate control. First and second inputs are independently coupled to the top and bottom gates of the transistor. The drain is coupled to an output and precharged to a low voltage. An input to either the top or bottom gates results in a high voltage to the drain and an output value of 1.

REFERENCES:
patent: 3755012 (1973-08-01), George et al.
patent: 4300064 (1981-11-01), Eden
patent: 4360897 (1982-11-01), Lehovec
patent: 4468574 (1984-08-01), Engeler et al.
patent: 5273921 (1993-12-01), Neudeck et al.
patent: 5349228 (1994-09-01), Neudeck et al.
patent: 5436506 (1995-07-01), Kim et al.
patent: 5677550 (1997-10-01), Lee
patent: 5773331 (1998-06-01), Solomon et al.
patent: 6064589 (2000-05-01), Walker
patent: 6072354 (2000-06-01), Tachibana et al.
patent: 6097221 (2000-08-01), Sako
patent: 6104068 (2000-08-01), Forbes
patent: 6188243 (2001-02-01), Liu et al.
patent: 6248626 (2001-06-01), Kumar et al.
patent: 6365465 (2002-04-01), Chan et al.
patent: 6376317 (2002-04-01), Forbes et al.
patent: 6404237 (2002-06-01), Mathew et al.
patent: 6420905 (2002-07-01), Davis et al.
patent: 6433609 (2002-08-01), Voldman
patent: 6472258 (2002-10-01), Adkisson et al.
patent: 6483156 (2002-11-01), Adkisson et al.
patent: 6506638 (2003-01-01), Yu
patent: 6518127 (2003-02-01), Hshieh et al.
patent: 6580137 (2003-06-01), Parke
patent: 2001/0022521 (2001-09-01), Sasaki et al.
patent: 2002/0047727 (2002-04-01), Mizuno
patent: 2002/0081808 (2002-06-01), Forbes
patent: 2002/0084803 (2002-07-01), Mathew et al.
patent: 2002/0093053 (2002-07-01), Chan et al.
patent: 2002/0105039 (2002-08-01), Hanafi et al.
patent: 2002/0140039 (2002-10-01), Adkisson et al.
patent: 2002/0153587 (2002-10-01), Adkisson et al.
patent: 2002/0180486 (2002-12-01), Yamashita et al.
patent: 2002/0187610 (2002-12-01), Furukawa et al.
patent: 2003/0058001 (2003-03-01), Boerstler et al.
patent: 2003/0089930 (2003-05-01), Zhao
patent: 2004/0083435 (2004-04-01), Gunderson et al.
Assaderaghi et al., “A Dynamic Threshold Voltage MOSFET (DTMOS) for Very Low Voltage Operation,” IEEE Electron Device Letters, vol. 15, No. 12, Dec. 1994, pp. 510-512.
Assaderaghi et al., “A Dynamic Threshold Voltage MOSFET (DTMOS) for Ultra-Low Voltage Operation,” Department of Electrical Engineering and Computer Science, University of California at Berkeley, Berkeley, CA, pp. 33.1.1-33.1.4.
Hsu et al., “Low-Frequency Noise Properties of Dynamic-Threshold (DT) MOSFET's,” IEEE Electron Device Letters, vol. 20, No. 10, Oct. 1999, pp. 532-534.
Wong, H.-S. Philip, “Field Effect Transistors—From Silicon MOSFETs to Carbon Nanotube FETs,” Proc, 23rdInternational Conference on Microelectronics (Miel 2002), vol. 1, NIS, Yugoslavia, May 12-15, 2002, pp. 103-107.
Brown et al., “Intrinsic Fluctuations in Sub 10-nm Double-Gate MOSFETs Introduced by Discreteness of Charge and Matter,” IEEE Transactions on Nanotechnology, vol. 1, No. 4, Dec. 2002, pp. 195-200.
Denton et al., “Fully Depleted Dual-Gated Thin-Film SOI P-MOSFET's Fabricated in SOI Islands with an Isolated Buried Polysilicon Backgate,” IEEE Electron Device Letters, vol. 17, No. 11, Nov. 1996, pp. 509-511.
Doris et al., “Extreme Scaling with Ultra-Thin Si Channel MOSFETs,” IBM Semiconductor Research and Development Center (SRDC), Microelectronics Division, Hopewell Junction, NY 12533, pp. 10.6.1-10.6.4.
Choi et al., “Nanoscale Ultrathin Body PMOSFETs With Raised Selective Germanium Source/Drain,” IEEE Electron Device Letters, vol. 22, No. 9, Sep. 2001, pp. 447-448.
Uchida et al., “Experimental Evidences of Quantum-Mechanical Effects on Low-field Mobility, Gate-channel Capacitance, and Threshold Voltage of Ultrathin Body SOI MOSFETs,” Advanced LSI Technology Laboratory, Toshiba Corp., 8 Shinsugita-cho, Isogo-ku Yokohama 235-8522, Japan, pp. 29.4.1-29.4.4.
Ren et al., “An Experimental Study on Transport Issues and Electrostatics of Ultrathin Body SOI pMOSFETs,” IEEE Electron Device Letters, vol. 23, No. 10, Oct. 2002, pp. 609-611.
Colinge et al., “Silicon-On-Insulator ‘Gate-All-Around Device’,” IMEC, Kapeldreef 75, 3030 Leuven, Belgium, pp. 25.4.1-25.4.4.
Hergenrother et al., “50 nm Vertical Replacement-Gate (VRG) nMOSFETs with ALD HfO2and Al2O3Gate Dielectrics,” Agere System, Murray Hill, NJ 07974, USA, pp. 3.1.1-3.1.4.
Hokazono et al., “14 nm Gate Length CMOSFETs Utilizing Low Thermal Budget Process with Poly-SiGe and Ni Salicide,” SoC Research & Development Center, Process & Manufacturing Engineering Center,2System LSI Division, Toshiba Corporation Semiconductor Company, 8 Shinsugita-cho, Isogo-ku, Yokohama, Kanagawa 235-8522, Japan, pp. 27.1.1-27.1.4.
Schulz et al., “50-nm Vertical Sidewall Transistors With High Channel Doping Concentrations,” Infineon Technologies AG, Corporate Research, D-81730 Munich, Germany, pp. 3.5.1-3.5.4.
Fung et al., “Gate length scaling accelerated to 30nm regime using ultra-thin film PD-SOI Technology,” IBM Microelectronics Semiconductor Research and Development Center (SRDC), pp. 29.3.1-29.3.4.
Narasimha et al., “High Performance Sub-40nm CMOS Devices on SOI for the 70nm Technology Node,” IBM Microelectronics Semiconductor Research and Development Center (SDRC), Hopewell Junction, NY 12533, USA, pp. 29.2.1-29.2.4.
Hisamoto, Digh, “FD/DG-SOI MOSFET—a viable approach to overcoming the device scaling limit,” Central Research Laboratory, Hitachi Ltd., Kokubunji, Tokyo 185-8601, Japan, pp. 19.3.1-19.3.4.
Kedzierski et al., “Complementary silicide source/drain thin-body MOSFETs for the 20nm gate length regime,” Department of Electrical Engineering and Computer Sciences, Univeristy of California at Berkeley, Berkeley, CA, 94720, USA, pp. 3.4.1-3.4.4.
Oh et al., “50 nm Vertical Replacement-Gate (VRG) pMOSFETs,” Bell Laboratories, Lucent Technologies, Murray Hill, NJ 07974, USA, pp. 3.6.1-3.6.4.
Pidin et al., “A Notched Metal Gate MOSFET for sub-0.1 μm Operation,” Fujitsu Laboratories Ltd., 10-1 Morinosato-Wakamiya, Atsugi 243-0197, Japan, pp. 29.1.1-29.1.4.
Tavel et al., “High Performance 40nm nMOSFETs With HfO2Gate Dielectric and Polysilicon Damascene Gate,” France Telecom R&D, B.P. 98, 38243 Meylan, France, pp. 17.1.1-17.1.4.
Krivokapic et al., “Nickel Silicide Metal Gate FDSOI Devices with Improved Gate Oxide Leakage,” AMD, Technology Research Group, M/S 143, One AMD Place, Sunnyvale, CA 94088-3453, USA, pp. 10.7.1-10.7.4.
Monfray et al., “SON (Silicon-On-Nothing) P-MOSFETs with totally silicided (CoSi2) Polysilicon on 5nm-thick Si-films: The simplest way to integration of Metal Gates on thin FD channels,” ST Microelectronics, 850, rue J.Monnet, 38921 Crolles, France, pp. 10.5.1-10.5.4.
Yang et al., “25 nm CMOS Omega FETs,” Taiwan Semiconductor Manufacturing Company, No. 6, Li-Hsin Rd. 6, Science-Based Industrial Park, Hsin-Chu, Taiwan, ROC, pp. 10.3.1-10.3.4.
Wong et al., “Design and Performance Considerations for Sub-0.1 μm Double-Gate SOI MOSFET's,” I.B.M. Thomas J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598, U.S.A., pp. 30.6.1-30.6.4.
Wong et al., “Device Design Considerations for Double-Gate, Ground-Plane, and Single-Gated Ultra-Thin SOI MOSFET's at the 25 nm Channel Length Generation,” IBM T.J. Watson Research Center, P.O. Box 218, Yorktown Heights, New York 10598, U.S.A., pp. 15.2.1-15.2.4.
Guarini et al., “Triple-Self-Aligned, Planar Double-Gate MOSFETs: Devices and Circuits,” IBM T.J. Watson Research Center, Yorktown Heights, New York 10598, U.S.A., pp. 19.2.1-19.2.4.
Solomon et al., “Two Gates Are Better Than One,” IEEE Circuits & Devices Magazine, Jan. 2003, pp. 48-63.
Cheng et al., “The Impact of High-κ Gate Die

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