Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1999-04-30
2002-10-01
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S365000
Reexamination Certificate
active
06459123
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to transistors and more particularly to field effect transistors having gates on opposite sides of the gate channel region of the transistor.
As is known in the art, a field effect transistor FET includes a gate channel region disposed between a source region and a drain region. A voltage applied to a gate electrode controls the flow of carriers passing through the gate channel between the source and drain regions. It is desirable to minimize the surface area used to form such a FET.
SUMMARY OF THE INVENTION
In accordance with one embodiment of the invention, a semiconductor body is provided having a transistor with a gate channel region disposed between a source region and a drain region. The regions are disposed in the body and extending vertically beneath a surface of the body. A pair of dielectric layers is provided, each one thereof being disposed on a corresponding one of a pair of opposing surface portions of the gate channel region. A pair of gate electrodes is provided, each one thereof being disposed on a corresponding one of the pair of dielectric layers.
In accordance with another embodiment, a semiconductor body is provided having formed therein a pair of transistors. Each one of the transistors has a gate channel region disposed between a source region and a drain region. The regions are horizontally separated by a common region extending vertically beneath a surface of the body. A plurality dielectric layers is provided, each one thereof being disposed on opposing surface portions of each one of the pair of gate channel regions.
A plurality of gate electrode conductive regions is provided, a first one thereof being disposed on a corresponding one of the plurality of dielectric layers.
In one embodiment, one of the plurality of gate conductor regions is disposed in the common region and provides a common gate conductor region for the pair of transistors.
In accordance with another embodiment, an insulating layer extending horizontally beneath the surface of the semiconductor body such insulating layer being disposed beneath the pair of transistors.
In accordance with another embodiment, the pair of transistors are CMOS transistors.
In accordance with another embodiment, an Synchronous Dynamic Random Access Memory (SRAM) array is provided. The array includes a plurality of SRAM cells arranged in rows and columns, each one of the cells having a WORDLINE connected to a WORDLINE CONTACT. The WORDLINE CONTACT is common to four contiguous one of the cells.
In accordance with another embodiment, each one of the cells having a plurality of electrically interconnected MOS transistors arranged to provide an SRAM circuit. Each one of the cells has a VDD CONTACT and a VSS CONTACT. One of such CONTACTs is disposed centrally within each one of the cells and the other one of the CONTACTs being common to four contiguous ones of the cells.
In accordance with another embodiment, each one of the cells has the common one of the CONTACTs and the WORDLINE CONTACT disposed at peripheral, corner regions of the cell.
In accordance with another embodiment, a method is provided for forming a transistor in a semiconductor body. The method includes forming a layer of material having a predetermined vertical thickness over a horizontal surface portion of the semiconductor body. Using the layer of material as a mask, a trench is etched into unmasked portions of the semiconductor body. A source, drain, and gate channel region is formed in a portion of the semiconductor body masked by the layer of material.
In accordance with another embodiment, a gate insulator is formed on a sidewall of the trench. Further, a gate conductors is formed in the trench.
In accordance with another embodiment, a method for forming a transistor in a semiconductor body is provided. The method includes forming a layer of material having a predetermined vertical thickness over a horizontal surface portion of the semiconductor body. Using the layer of material as a mask, a trench is into unmasked portions of the semiconductor body. A source, drain, and gate channel region is formed in a vertical relationship in the surface portion of the semiconductor portion of the semiconductor body masked by the layer of material. Gate conductors are formed over opposite sides of the gate channel region.
In accordance with another embodiment, a method is provided for forming a transistor in a semiconductor body. The method includes patterning a covering material along a horizontal surface of the semiconductor body to provide such material with a vertically extending sidewall portion. A layer of material with a predetermined thickness is conformally deposited a over the horizontal surface of the covering material and over the vertically extending sidewall portion of the covering material to provide a vertically extending portion of such layer of material. The layer of material is anisotropically etched to remove the portion of such material deposited over the horizontal surface portion of the covering material while leaving the vertically extending portion of such layer of material. Using the vertically extending portion of the layer of material as a mask, a trench is etched into unmasked portions of the semiconductor body. A source, drain, and gate channel region is formed in a portion of the semiconductor body masked by the vertically extending portion of the layer of material.
REFERENCES:
patent: 4670768 (1987-06-01), Sunami et al.
patent: 5181088 (1993-01-01), Mikata et al.
patent: 5376814 (1994-12-01), Lee
patent: 5550396 (1996-08-01), Tsutsumi
patent: 5656842 (1997-08-01), Iwamatsu et al.
patent: 5670803 (1997-09-01), Beilstein, Jr. et al.
Co-Pending Patent Application No. 09/302,757 filed Apr. 30, 1999 and assigned to Art Unit 2822.
Enders Gerhard
Risch Lothar
Schulz Thomas
Widmann Dietrich
Braden Stanton
Chaudhuri Olik
Infineon Technologies Richmond LP
Peralta Ginette
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