Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-04-24
2001-07-17
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S304000, C257S330000, C257S331000, C257S333000, C257S334000, C257S335000, C257S374000, C257S395000, C257S396000, C257S397000
Reexamination Certificate
active
06262453
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to the structure and fabrication process of a trenched DMOS power device. More particularly, this invention relates to a novel trenched DMOS device structure and fabrication process with double gate-oxide structure to reduce the gate/drain capacitance. The switching speed of the trenched DMOS device is improved without degrading the breakdown voltage. Also, a low threshold voltage is maintained by controlling the thickness of a thin-gate-oxide layer. Furthermore, the drain-to-source resistance is decreased by forming a high-dopant-concentration N+ buried-region without significantly increasing the drain-to-gate capacitance.
2. Description of the Prior Art
Several difficulties are faced by those involved in the technology to further increase the cell density of a power DMOS transistor in order to achieve a lower on resistance and meanwhile attempting to increase the DMOS switching speed.
FIG. 1
shows a DMOS prior art DMOS trench device
10
supported on a N+ substrate and an N-epitaxial layer. The DMOS device
10
includes trenched-gates
30
formed in the trenches filled with polysilicon and surrounded by body regions
20
and covered by an insulation layer
45
. Each transistor cell further includes a N+ source region encompassed in the body region
20
disposed near the top surface of the substrate and right next to the trenched gates
30
. The body region
20
further includes a high concentration P+ body dopant region
60
for reducing the contact resistance with the source contact metal
70
. The source contact metal
70
contact the source regions
40
through openings in the insulation layer
45
. The body regions
20
are formed with a depth less than the depth of the trenched-gate
30
. The gate oxide uniformly grows along the trench sidewall. However, the device now faces the difficulty of increasing gate/drain capacitance as cell density increases. Moreover, early breakdown near the bottom of the trenched gates becomes a design concern if the gate oxide is not thick enough. Due to this limitation, a higher cell density of the DMOS power device with low gate/drain capacitance cannot be easily achieved. A conventional method is to increase the thickness of the gate oxide layer near. However, a gate-oxide layer with greater thickness will often affect the threshold voltage.
Therefore, a need still exits in the art of power device fabrication, particularly for trenched DMOS design and fabrication, to provide a structure and fabrication process that would resolve these difficulties. More specifically, it is preferably that a transistor with a high cell density can be produced with effective prevention against early breakdown without increasing the device threshold voltage. It is further desirable to reduce the gate charges between gate/drain such that the device switching speed can be improved.
SUMMARY OF THE PRESENT INVENTION
It is therefore an object of the present invention to provide a new DMOS fabrication process and a new device structure. Those of ordinary skill in the art of trenched DMOS fabrication will be enabled to reduce gate-to-drain capacitance to achieve higher device switching speed. Meanwhile, the technical difficulty of breakdown voltage degradation is resolved without causing higher threshold voltage due to a thicker gate-oxide. The performance characteristics of the trenched DMOS device are improved such that aforementioned limitations and difficulties as encountered in the prior art can be overcome.
Specifically, it is an object of the present invention to provide an novel trenched DMOS structure and fabrication process with a double-gate-oxide structure under the gate to form champagne-glass shaped gates. The double gate-oxide structure includes a thick-gate-oxide covering the trench walls at the lower portion of the gates. The thick-oxide has a thickness about two-to-four time's thickness of the thin-gate-oxide layer covering the trench-walls on the upper portion of the trenched gates to prevent threshold voltage from increasing due to process variation causing p body diffusion into the thick oxide area. An early breakdown is prevented while the gate/drain capacitance is reduced with improved switching speed.
Another object of the present invention is to provide a novel trenched DMOS structure and fabrication process wherein the DMOS transistor is provided a double-gate-oxide structure under the gate to form champagne-glass shaped gates. The trenched DMOS device is further provided with a shallow lightly doped body region to reduce the threshold voltage. Therefore, thick-gate-oxide layer covering the trench walls near the bottom portion is implemented to prevent early breakdown and to increase the switch speed without adversely increasing the threshold voltage.
Another object of the present invention is to provide an improved trench DMOS structure and fabrication process wherein the DMOS transistor is provided with a double-gate-oxide structure under the gate to form champagne-glass shaped gates. The shallow lightly doped body region is further formed with less depth than the source regions. Therefore, shallow lightly doped body region is implemented to reduce the threshold voltage threshold voltage without causing a punch through problem by limiting the depth of the shallow lightly doped body region.
Another object of the present invention is to provide an improved trench DMOS structure and fabrication process wherein the DMOS transistor is provided with a double-gate-oxide structure under the gate to form champagne-glass shaped gates. A high dopant-concentration buried region is formed a distance below the trenched gate between the bottom of the trenched gate and the N+ substrate. The gate-to-drain capacitance is kept substantially unchanged while the source-to-drain resistance is decreased.
Briefly, in a preferred embodiment, the present invention discloses a DMOS transistor cell formed in a semiconductor substrate with a heavily doped first conductivity type as a drain region. The transistor cell includes a epitaxial layer doped with impurities of a first conductivity type, lying on the semiconductor substrate. The transistor cell further includes a gate disposed in a trench padded with a double-gate-oxide structure having a thick-gate-oxide covering trench walls on a lower portion of the trench and a thin-gate-oxide cover trench walls on an upper portion of the trench. The trench is opened vertically downward from the top surface disposed substantially in a center portion of the transistor cell with bottom surface lies above the heavily doped substrate. The gate is defined by a polysilicon layer disposed the trench insulated from the substrate by the double-gate-oxide structure thus defining a champagne glass shaped gate. The transistor cell further includes a source region disposed in the substrate surrounding an upper portion of the trench. The transistor cell further includes a body region doped with impurities of a second conductivity type in the substrate surrounding the source region and the trench gate therein. The body region extends vertically downward to a thin gate oxide/thick gate oxide boundary of the transistor cell wherein the body region providing a channel for transmitting a current therein from the source region to the drain along a substantially vertical direction. The transistor cell further includes a high-dopant-concentration substrate-type buried region disposed at a distance below the trenched gate for decreasing the source-to-drain resistance Rds without significantly increasing the gate-to-drain capacitance.
In a preferred embodiment, the transistor cell further includes a shallow lightly doped body region in an upper portion of the body region. The shallow lightly doped body region has a depth slightly greater than the source region. The shallow lightly doped body region is doped with a lower concentration of impurities of the second conductivity type than the body region to reduce a threshold volta
Lee Eddie C.
Lin Bo-In
MagePower Semiconductor Corp.
Warren Matthew E.
LandOfFree
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