Double-Gate FETs (field effect transistors)

Details Double-Gate FETs (field effect transistors) Double-Gate FETs (field effect transistors)

2006-08-08

2006-08-08

Flynn, Nathan J. (Department: 2826)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S213000, C257S288000, C257SE27112

Reexamination Certificate

active

07087966

ABSTRACT:
A semiconductor structure and method for forming the same. The structure includes multiple fin regions disposed between first and second source/drain (S/D) regions. The structure further includes multiple front gates and back gates, each of which is sandwiched between two adjacent fin regions such that the front gates and back gates are alternating (i.e., one front gate then one back gate and then one front gate, and so on). The widths of the front gates are greater than the widths of the back gates. The capacitances of between the front gates and the S/D regions are smaller than the capacitances of between the back gates and the S/D regions. The distances between the front gates and the S/D regions are greater than the distances between the back gates and the S/D regions.

REFERENCES:
patent: 6300182 (2001-10-01), Yu
patent: 6433609 (2002-08-01), Voldman
patent: 6720619 (2004-04-01), Chen et al.
Anil, K.G., et al.; Layout density analysis of FinFETs; IEEE 2003; pp. 139-142; 0-7803-79999-3/03.
Ludwig, T., et al.; FinFET technology for future microprocessors; IEEE 2003; pp. 33-34; 0-7803-7815-6/03.
Ieong, M., et al.; High performance double-gate device technology challenges and opportunities; IEEE 2002; pp. 492-495; 0-7695-1561-4/02.
Fu-Liang Yang, et al.; A 65nm node strained SOI technology with slim spacer; IEEE 2003; pp. 27.2.1-27.2.4; 0-7803-7872-05/03.

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