Double-gate fet with planarized surfaces and self-aligned...

Details Double-gate fet with planarized surfaces and self-aligned... Double-gate fet with planarized surfaces and self-aligned...

2005-11-22

2005-11-22

Loke, Steven (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S347000, C257S350000, C257S351000, C438S157000, C438S283000

Reexamination Certificate

active

06967377

ABSTRACT:
It is, therefore, an object of the present invention to provide a structure and method for an integrated circuit comprising a first gate, a second gate, and source and drain regions adjacent the first and second gates, wherein the structure has a planar upper structure and the first gate, source and drain regions are silicided in a single self-aligned process (salicide).

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“Self-Aligned (Top and Bottom) Double-Gate MOSFET with a 25 nm Thick Silicon Channel”, Hon-Sum Philip Wong, Kevin K. Chan, and Yuan Taur, IBM Thomas J. Watson Research Center, Yorktown Heights, NY, IEEE 1997, pp. 427-430.
New Planar Self-Aligned Double-Gate Fully-Depleted P-MOSFET's Using Epitaxial Lateral Overgrowth (ELO) and Selectively Grown Source/Drain (S/D), Taichi Su, John P. Denton, and Gerold W. Neudeck, IEEE School of Electrical and Computer Engineering, Perdue University, West Lafayette, IN, IEEE, 2000, pp. 110-111.

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