Double gate DRAM memory cell having reduced leakage current

Details Double gate DRAM memory cell having reduced leakage current Double gate DRAM memory cell having reduced leakage current

2003-01-24

2003-12-09

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Systems using particular element

Capacitors

C251S071000, C251S297000, C251S296000, C251S306000, C251S311000

Reexamination Certificate

active

06661702

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices, and more particularly to dynamic random access memory (DRAM) storage cells and arrays.
BACKGROUND OF THE INVENTION
A dynamic random access memory (DRAM) includes a large number of memory cells, each of which can store at least one bit of data. The memory cells are arranged in an array having a number of rows and columns. Memory cells within the same row are commonly coupled to a word line and memory cells within the same column are commonly coupled to a bit line. The memory cells within the array are accessed according to various memory device operations. Such operations include read operations, write operations and refresh operations.
In a typical memory cell read operation, an external memory address is applied which results in the activation of a word line. When activated, the word line couples the data stored within the memory cells of its respective row to the bit lines of the array. In typical DRAM, the coupling of memory cells results in a differential voltage appearing on a bit line (or bit line pair). The differential voltage is amplified by a sense amplifier, resulting in amplified data signals on the bit lines. The applied memory address also activates column decoder circuits, which connect a given group of bit lines to input/output circuits. Commonly, the memory address is multiplexed, with a row address being applied initially to select a word line, and a column address being applied subsequently to select the group of bit lines.
The typical DRAM memory cell stores data by placing charge on, or removing charge from, a storage capacitor. Over time, this charge is reduced by way of a leakage current. Thus, it is important for the DRAM to restore the charge on the capacitor before the amount of charge falls below a critical level, due to leakage mechanisms. Restoration of charge is accomplished with a refresh operation.
The critical level of charge for a storage capacitor is determined by the sensitivity of the memory device sense amplifiers. The storage capacitor must have enough charge to create a sufficient differential voltage for the sense amplifier to reliably sense, without producing an erroneous output. The time needed before the charge on the capacitor falls below the critical level is commonly referred to as the maximum “pause” period. A DRAM must perform a refresh operation on every row in the device before that row experiences the maximum “pause” period. Read operations and write operations will also serve to refresh the memory cells of a row.
As DRAMs are being used in battery operated applications, such as laptop computers, it is crucial to reduce the power consumed by DRAMs, and thus allow a longer battery lifetime for battery operated systems. Every refresh operation a DRAM must perform consumes a considerable amount of power. This power is wasted because it is not typically performed to transfer data to or from the DRAM for the system's needs. The refresh operation is used only to sustain the data integrity in the DRAM. Thus, it is important to reduce the number of refresh operations needed over time. One way of achieving this goal is to reduce the rate of charge leakage from the storage capacitor.
To better understand the distinguishing features and advantages of the present invention, a prior art DRAM will be discussed. Referring now to
FIG. 1
, a DRAM array is set forth and designated by the general reference character
100
. The DRAM array
100
is arranged as an n×m array, having n rows and m columns. The DRAM array
100
includes a word line driver bank
102
coupled to n sets of word lines (WL
0
-WLn), as well as a sense amplifier bank
104
, coupled to m sets of bit line pairs (BL
0
, BL
0
_-BLm, BLm_). A memory cell is formed where a word line intersects a bit line pair. The memory cells are designated as M
00
-Mnm, where the first digit following the “M” represents the physical row of the memory cell's location, and the second digit represents the physical column of the memory cell's location. For example, M
00
is the memory cell located at the intersection of WL
0
and bit line pair BL
0
, BL
0
_. Each memory cell (M
00
-Mnm) contains a pass transistor (shown as n-channel MOSFETs Q
00
-Qnm) and a storage capacitor (shown as C
00
-Cnm). Each memory cell further includes a storage node
106
-
112
formed at the junction of the source of the pass transistor (Q
00
-Qnm) and its associated storage capacitor (C
00
-Cnm).
The word line driver bank
102
is separated into n separate word line driver circuits shown as DRV
0
-DRVn. The word line driver bank
102
is responsive to a row address (not shown) such that only one word line driver circuit (DRV
0
-DRVn) will drive its corresponding word line high according to the row address received. For example, word line driver circuit DRV
0
will drive word line WL
0
high when the row address value of “zero” is received, and word line driver circuit DRVn will drive word line WLn high when the row address value of “n” is received.
The sense amplifier bank
104
is separated into m separate sense amplifier circuits, shown as SA
0
-SAm. For reasons discussed below, while all of the sense amplifiers
104
will be activated simultaneously, only selected of the sense amplifiers in the sense amplifier bank
104
will pass its sensed data to the DRAM output (not shown). A sense amplifier (SA
0
-SAm) will be selected according to the column address (not shown) applied to a column decoder (also not shown) in the DRAM.
Data is stored in the DRAM array
100
by placing or removing charge from the storage capacitors (C
00
-Cnm). In a write cycle, a row address is applied to the DRAM and will activate a word line. In this example assume a logic value “1” is to be written into memory cell M
00
. Word line driver circuit DRV
0
within the word line driver bank
102
will raise word line WL
0
to a high logic level. A column address will couple write circuitry (not shown) to bit line BL
0
to allow a high logic level to be written into storage cell M
00
. The high logic level will be stored in memory cell M
00
at storage node
106
by placing charge on storage capacitor C
00
. In order to ensure maximum charge is placed on the storage capacitor, word line driver circuit DRV
0
will raise word line WL
0
to a voltage level that is at least one n-channel threshold voltage (Vtn) above the voltage level applied to bit line BL
0
during the write cycle.
Once storage node
106
reaches a high logic level, which is typically equal to the high power supply voltage (Vcc) of the DRAM array
100
, the DRAM is allowed to go into a precharge state in which word line WL
0
will be driven to a low logic level, for example the low power supply voltage (Vss). In this state, the storage node
106
will be isolated from the bit line BL
0
as the pass transistor Q
00
will be in a non-conducting state.
Because the leakage characteristics of the storage capacitor C
00
and pass transistors Q
00
are not ideal, once the storage node
106
becomes isolated from the bit line BL
0
, the charge stored on the storage capacitor C
00
will leak away, and the voltage will slowly be reduced. As mentioned previously, the charge on the storage capacitor C
00
must be restored before the charge level falls below the critical level. This helps to ensure that the data will be reliably sensed by sense amplifier SA
0
. The data may be restored during either a read operation or a refresh operation, as determined by control signals (not shown) that may be applied to the DRAM. In both cases, the data of a complete row of DRAM cells will be restored.
In order to restore the data in the row formed by word line WL
0
, word line driver WL
0
will be activated, raising word line WL
0
at least one Vtn above the DRAM array
100
high power supply voltage Vcc. As a result, the pass transistors connected to word line WL
0
are turned on, coupling the storage nodes of the row to their respective bit lines BL
0
-BLm. This creates a differential voltage across the

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