Double-ended memory cell array using interleaved bit lines and m

Details Double-ended memory cell array using interleaved bit lines and m Double-ended memory cell array using interleaved bit lines and m

1989-08-24

1991-02-12

Hecker, Stuart N.

Static information storage and retrieval

Systems using particular element

Flip-flop

365205, 365 63, G11C 1140

Patent

active

049929810

ABSTRACT:
The memory cell array is one in which the bit lines associated with each column of double-ended memory cells are interleaved with the bit lines of adjacent columns of memory cells. Because the spacing of metallic bit lines is governed by certain ground rules, cell length in the x-dimension could be reduced no further as long as metallic interconnections were used. To overcome the spacing limitation of metallic interconnections, polycrystalline fingers or extensions are substituted for metal cross-coupling interconnections. The latter in conjunction with metallic straps which are shorter than the widths and spacing of two metallic interconnection lines provides a significant reduction in the x-dimension and hence in cell area. The method and structure taught may be utilized with both bipolar and unipolar devices.

REFERENCES:
patent: 4158237 (1979-06-01), Wiedmann
patent: 4425574 (1984-01-01), Silvestri et al.
patent: 4445201 (1984-04-01), Pricer
patent: 4476547 (1984-10-01), Miyasaka
patent: 4586171 (1986-04-01), Fujishima
patent: 4709351 (1987-11-01), Kajigaya
patent: 4916661 (1990-04-01), Nawaki et al.
patent: 4922459 (1990-05-01), Hidaka
IEEE Journal of Solid-State Circuits vol. SC-16 No. 5, Oct. 1981, p. 429, "High Speed Split-Emitter I.sup.2 L/MTL Memory Cell", by S. K. Wiedmann et al.

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