Double-doped polysilicon floating gate

Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode

Reexamination Certificate

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C257SE29300

Reexamination Certificate

active

07956402

ABSTRACT:
The present invention provides a method and apparatus for forming a double-doped polysilicon floating gate in a semiconductor memory element. The method includes forming a first dielectric layer on a semiconductor substrate and forming a floating gate above the first dielectric layer, the floating gate comprised of a first layer doped with a first type of dopant material and a second layer doped with a second type of dopant material that is opposite the first type of dopant material in the first layer. The method further includes forming a second dielectric layer above the floating gate, forming a control gate above the second dielectric layer, and forming a source and a drain in the substrate.

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Horiguchi, et al. “Retention Time Enhancement in Direct Tunneling Memory (DTM) Utilizing Floating Gate Depletion by Diffusion Stopper” pp. 458-458.3.
Muller, et al., Device Electronics for Integrated Circuits, 2ndEdition, 1986, John Wiley & Sons, New York, pp. 80.

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