Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2000-03-15
2001-10-23
Wojciechowicz, Edward (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S335000, C257S339000, C257S343000, C257S408000
Reexamination Certificate
active
06307224
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and particularly, to a planar field effect semiconductor device having a high withstand voltage.
2. Description of the Related Art
FIG. 6A
is a sectional view partly showing a MOSFET (metal oxide semiconductor field effect transistor) as a part of a semiconductor power device according to a prior art. This MOSFET is an n-channel planar double diffused MOSFET (DMOSFET) formed on an SOI (semiconductor on insulator) substrate.
The SOI substrate consists of a semiconductor substrate, an insulator layer formed on the semiconductor substrate, and a semiconductor layer (SOI layer) formed on the insulator layer. On the SOI layer, necessary elements are formed. When a device is formed on the SOI substrate, the insulator layer under the SOI layer is advantageous in isolating the elements from one another. Compared with isolation by p-n junctions, isolation by the insulator layer in the SOI substrate is more advantageous because it causes smaller parasitic capacitance or parasitic operation. Due to this, SOI substrates are frequently used for planar MOSFETs.
In
FIG. 6A
, the conventional SOI substrate on which the n-channel planar MOSFET is formed consists of a p
−
-type semiconductor substrate
111
, an insulator layer
112
formed on the substrate
111
, and an n
31
-type SOI layer
113
formed on the insulator layer
112
. In a surface area of the SOI layer
113
, a p-type impurity diffusion region
114
is formed. In a surface area of the diffusion region
114
, and n
+
-type source region
116
is formed and is electrically connected to a source electrode S. On the diffusion region
114
, an oxide film
117
is formed to extend between the source region
116
and the SOI layer
113
. On the gate oxide film
117
, a gate electrode
118
is formed.
An n
+
-type drain region
121
is formed in a surface area of the SOI layer
113
and is connected to a drain electrode D. The drain region
121
is separated from the diffusion region
114
by a distance L
0
. During operation, the surface of the diffusion region
114
under the gate electrode
118
is inverted electrically to form a n-channel.
A p
+
-type impurity diffusion region
115
may be formed in a surface area of the diffusion region
114
. The diffusion region
115
is electrically connected to the source electrode S, to fix the potential of the diffusion region
114
at the potential of the source electrode S. This stabilizes the threshold characteristics of the MOSFET more than electrically floating the diffusion region
114
.
FIG. 6B
shows depletion layers formed in the SOI layer
113
when the MOSFET is reversely biased. The conventional n-channel MOSFET extends a depletion layer d
01
around a p-n junction, to relax an electric field and improve the breakdown resistance of the MOSFET. To form depletion layers in the SOI layer
113
, the conventional MOSFET decreases an impurity concentration in the SOI layer
113
.
On the same substrate where the n-channel MOSFET is formed, a p-channel MOSFET may be formed to provide a CMOS (complementary MOS) structure.
FIG. 7A
shows such a p-channel planar MOSFET formed on the same substrate where the n-channel MOSFET is present.
Namely, the p-channel MOSFET is formed on the SOI substrate that consists of the p
−
-type semiconductor substrate
111
, the insulator layer
112
formed on the substrate
111
, and the n
−
-type SOI layer
113
formed on the insulator layer
112
. In the surface area of the SOI layer
113
, there are p
+
-type source region
124
electrically connected to a source electrode S, an n-type impurity diffusion region
130
serving as a channel region, and a p
−
-type LDD (lightly doped drain) region
127
. The regions
124
,
130
, and
127
are formed close to one another. On the diffusion region
130
, a gate oxide film
125
is formed to extend between the source region
124
and the LDD region
127
. On the gate oxide film
125
, a gate electrode
126
is formed. In a surface area of the LDD region
127
, a p
+
-type drain region
129
is formed and is connected to a drain electrode D. The drain region
129
is spaced from the diffusion region
130
by a predetermined distance.
An n
+
-type impurity diffusion region
123
may be formed adjacent to the source region
124
and is electrically connected to the source electrode S. This arrangement fixes the potential of the diffusion region
130
at the potential of the source electrode S through the SOI layer
113
, to stabilize the threshold characteristics of the MOSFET.
The p-channel MOSFET of the prior art employs the LDD region
127
to relax an electric field. Namely, the prior art forms an extensive depletion layer at a p-n junction formed around LDD region
127
, to relax an electric field and improve the breakdown resistance of the MOSFET.
FIG. 7B
shows depletion layers formed in the SOI layer
113
when the MOSFET is reversely biased. One depletion layer extends from the source region
124
to the drain region
129
and mainly spreads in the LDD region
127
. To extend depletion layers, the prior art decreases an impurity concentration in the LDD region
127
and horizontally elongates the LDD region
127
.
As mentioned above, in the n-channel MOSFET of
FIG. 6A
, it is required to form wider depletion layers in the SOI layer
113
during a reverse bias operation, to improve a withstand voltage. To achieve this and not to limit the depletion layers by the drain region
121
, the prior art forms the drain region
121
as far from the diffusion region
114
as possible.
This may improve the withstand voltage of the MOSFET. However, the long distance L
0
between the diffusion region
114
and the drain region
121
increases the area of the MOSFET and hinders high integration of elements in the semiconductor device. In addition, the long distance L
0
increases electric resistance in the SOI layer
113
, to increase the ON-resistance of the MOSFET.
To minimize the area of the MOSFET, the drain region
121
must be brought close to the edges of depletion layers. The drain region
121
has a high impurity concentration to secure an ohmic contact to the drain electrode D, and therefore, it suddenly stops depletion layers like a depletion layer d
03
in FIG.
6
B and generates impact ions that may break down the MOSFET. To avoid such a breakdown and absorb process variations, a sufficient margin must be included in the distance between depletion layers and the drain region
121
. This increases the area and ON-resistance of the MOSFET.
Like the n-channel MOSFET, in the case of the p-channel MOSFET of
FIG. 7A
, it is required to form depletion layers during a reverse bias operation, to improve a withstand voltage. To achieve this, the LDD region
127
must be long. Namely, the drain region
129
must be distanced away from the source region
124
. This increases the area of the MOSFET and hinders high integration of elements. Elongating the LDD region
127
increases electric resistance to increase the ON-resistance of the MOSFET.
In the p-channel MOSFET, when a depletion layer reaches the drain region
129
, the depletion layer is suddenly stopped by the drain region
129
due to a sudden change in impurity concentration, to generate impact ions that may break down the MOSFET. To avoid this and to absorb process variations, the distance between depletion layers and the drain region
129
must have a sufficient margin. This results in elongating the LDD region
127
, thereby increasing the area and ON-resistance of the MOSFET.
In this way, any of n- and p-channel MOSFETs of the prior art realizes a high withstand voltage only by increasing the area and ON-resistance thereof.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a semiconductor device capable of securing reduced dimensions and a high withstand voltage.
Another object of the present invention is to provide a semiconductor device capable of securing a stabi
Kabushiki Kaisha Toshiba
Oblon & Spivak, McClelland, Maier & Neustadt P.C.
Wojciechowicz Edward
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