Double diffused MOS transistor and method for manufacturing...

Details Double diffused MOS transistor and method for manufacturing... Double diffused MOS transistor and method for manufacturing...

2005-08-02

2005-08-02

Pham, Long (Department: 2814)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S339000, C257S341000, C257S365000

Reexamination Certificate

active

06924530

ABSTRACT:
A method of manufacturing a semiconductor device, such as a double-diffused metal oxide semiconductor (DMOS) transistor, where a first layer may be formed on a semiconductor substrate, with isolation trenches formed in the first layer and semiconductor substrate, and with the trenches being filled with an isolation layer. A second layer may be formed on the first layer and semiconductor substrate, and a plurality of drain trenches may be formed therein. A pair of plug-type drains may be formed in the trenches, to be separated from the isolation layer by a dielectric spacer. Gates and source areas may be formed on a resultant structure containing the plug-type drains. Accordingly, current may be increased with a reduction in drain-source on resistance, and an area of the isolation layer can be reduced, as compared to an existing isolation layer, potentially resulting in a reduction in chip area.

REFERENCES:
patent: 5682048 (1997-10-01), Shinohara et al.
patent: 5882966 (1999-03-01), Jang
patent: 6194761 (2001-02-01), Chiozzi et al.
patent: 6472709 (2002-10-01), Blanchard

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