Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2005-07-26
2005-07-26
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S328000, C257S332000
Reexamination Certificate
active
06921938
ABSTRACT:
A double diffused field effect transistor and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type. Next, at least one dopant species, also of the first conductivity type, is introduced into a surface of the substrate so that the substrate has a nonuniform doping profile. An epitaxial layer of the first conductivity type is formed over the substrate and one or more body regions of a second conductivity type are formed within the epitaxial layer. A plurality of source regions of the first conductivity type are then formed within the body regions. Finally, a gate region is formed, which is adjacent to the body regions.
REFERENCES:
patent: 5072266 (1991-12-01), Bulucea et al.
patent: 5701023 (1997-12-01), Bulucea et al.
patent: 5814858 (1998-09-01), Williams
patent: 5893742 (1999-04-01), Demirliogluy et al.
patent: 5897355 (1999-04-01), Bulucea et al.
patent: 5981344 (1999-11-01), Hshieh et al.
patent: 6084268 (2000-07-01), De Fresart et al.
patent: 6274464 (2001-08-01), Drobny et al.
Baliga, B. Jayant, Chapter 7, “Power Mosfet: 7.1 Basic Structure and Operation,” PWS Publishing (Boston, 1996), pp. 336-339.
Wolf, Stanley et al., “Silicon Processing for the VLSI Era”, vol. 1:Process Technology, Lattice Press, Sunset Beach, CA, (1986), pp. 321-323.
Wilson, Syd R., et al., “Handbook of Multilevel Metallization for Integrated Circuits,” Noyes Publ., Westwood, New Jersey, (1993), pp. 42-59; 867-872.
IBM Technical Disclosure Bulletin, “Fabrication of Narrow Self Aligned Trenches and Isolated N-Type Silicon Region With buried N+ Layer,” vol. 34, No. 10A, (Mar., 1992), pp. 397-399.
Gary E. McGuire, Semiconductor Materials and Process Technology Handbook, Noyes Publ., Norwich, New York, (1988), p. 18.
Hu, Chenning, “Optimum Doping Profile for Minimum Ohmic Resistance and High-Breakdown Voltage,” IEEE Transactions on Electron Devices, vol. ED-26, No. 3, Mar. 1979, pp. 243-244.
Grove, A. S., Physics and Technology of Semiconductor Devices, 3.7, “The Redistribution of Impurities in Epitaxial Growth,” pp. 78-83, John Wiley and Sons, Inc. New York, 1967.
General Semiconductor Inc.
Mayer Fortkort & Williams PC
Mayer, Esq. Stuart H.
Nelms David
Nguyen Thinh T
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